---
title: "Sequence detector 1011 using T flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-1011-t"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1011-t
site: BCT Engineering
---

# Sequence detector 1011 using T flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2080 Baisakh, 13 marks; 2076 Chaitra, 10 marks (asked 2 times)
- Video: [VLSI : sequence detector 1010 || sequence detector 1011 overlapping mealy FSM](https://www.youtube.com/watch?v=EUosQBSw2qQ) — VLSI-LEARNINGS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1011-t
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Consider a sequential detector that receives binary data stream at its input 'X' and signals when a serial sequence '1011' arrives at the input by making its output 'Y' high, otherwise output remains low. Design a sequence detector state machine using positive edge triggered T flip flops.

## Short answer

Use a Mealy machine with overlap and 2 T flip-flops. State assignment: A=00, B=01, C=10, D=11. T1 = Q1 Q0 X + Q1 Q0' X' + Q1' Q0 X', T0 = Q0 X' + Q0' X (T0 = Q0 XOR X), and output Y = Q1 Q0 X.

## Answer

The detector watches the serial data stream X and makes Y = 1 when the last four bits received are 1, 0, 1, 1; otherwise Y = 0. Positive-edge triggered T flip-flops are used.

A **Mealy** machine is used (output depends on the present state and the present input), and overlapping sequences are detected. Since the sequence has 4 bits, 4 states are needed, so **2 T flip-flops** ($Q_1Q_0$) are used, clocked on the positive edge. (A Moore machine would need 5 states.)

#### Step 1: States
| Present state | Meaning | Next (X=0) | Next (X=1) | Y (X=0) | Y (X=1) |
|---|---|---|---|---|---|
| A | reset / no useful bits | A | B | 0 | 0 |
| B | "1" received | C | B | 0 | 0 |
| C | "10" received | A | D | 0 | 0 |
| D | "101" received | C | B | 0 | 1 |

#### Step 2: State diagram
```text
 Main path (label = X/Y):
 A -1/0-> B -0/0-> C -1/0-> D -1/1-> B
 Other transitions:
 A -0/0-> A    B -1/0-> B
 C -0/0-> A    D -0/0-> C
```

#### Step 3: State assignment
| State | A | B | C | D |
|---|---|---|---|---|
| Q1 Q0 | 0 0 | 0 1 | 1 0 | 1 1 |

#### Step 4: Excitation table
T excitation: T = 1 when the flip-flop must change, T = 0 when it must hold ($T = Q \oplus Q^+$).

| Q1 Q0 | X | Q1+ Q0+ | T1 | T0 | Y |
|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | 0 | 0 |
| 0 0 | 1 | 0 1 | 0 | 1 | 0 |
| 0 1 | 0 | 1 0 | 1 | 1 | 0 |
| 0 1 | 1 | 0 1 | 0 | 0 | 0 |
| 1 0 | 0 | 0 0 | 1 | 0 | 0 |
| 1 0 | 1 | 1 1 | 0 | 1 | 0 |
| 1 1 | 0 | 1 0 | 0 | 1 | 0 |
| 1 1 | 1 | 0 1 | 1 | 0 | 1 |

#### Step 5: K-maps (rows $Q_1$, columns $Q_0X$)
| T1: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 |

| T0: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 |

| Y: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |

#### Step 6: Equations
$$
\begin{aligned} &T_1 = Q_1Q_0X + Q_1\overline{Q_0}\overline{X} + \overline{Q_1}Q_0\overline{X} \\ &T_0 = Q_0\overline{X} + \overline{Q_0}X \\ &Y = Q_1Q_0X \end{aligned}
$$

#### Step 7: Logic diagram
```text
   +-----+       +-----+
T0>|T   Q|-Q0 T1>|T   Q|-Q1
   | FF0 |       | FF1 |
   |     |       |     |
   +--^--+       +--^--+
      |             |
CLK---+-------------+
X = serial input, common to the gates
T1 = Q1.Q0.X + Q1.Q0'.X' + Q1'.Q0.X'
T0 = Q0.X' + Q0'.X
Y = Q1.Q0.X
```
The gates for each flip-flop input are built from the equations; the output gate gives Y directly (Mealy output).

#### Check with an input stream
| X | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
|---|---|---|---|---|---|---|---|---|---|---|
| State | A | A | B | C | D | B | C | D | B | C |
| Y | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |

Y = 1 appears exactly on the clock in which the last bit of 1011 arrives; overlapping sequences are also detected.

Note: $T_0 = Q_0 \oplus X$, so FF0 needs only one XOR gate.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How is T found in the 1011 detector?
   A. T = Q XOR Q+
   B. T = Q+
   C. T = Q AND Q+
   D. T = Q'
   Answer: A. T = 1 when the flip-flop must change and 0 when it must hold. (Key point: T excitation)

2. In state D ('101'), what happens on X = 0 and on X = 1?
   A. X=0 goes to C ('10'), X=1 goes to B with Y = 1
   B. X=0 goes to A, X=1 goes to C
   C. X=0 goes to B, X=1 goes to D
   D. X=0 goes to C with Y=1, X=1 goes to B
   Answer: A. 101 followed by 0 gives suffix 10 (state C); followed by 1 completes 1011 (Y = 1) and the last 1 is a new start, state B. (Key point: State D transitions)

3. What does 'overlapping sequences are detected' mean here?
   A. The detector ignores bits after a match
   B. The last bit(s) of one 1011 can start the next one
   C. Two detections cannot happen close together
   D. Y stays high for two clocks
   Answer: B. After a match the machine goes to B, keeping the final 1 as the start of the next possible sequence. (Key point: Overlap)

4. What is T0 for this design?
   A. T0 = Q0 XOR X
   B. T0 = Q0 X
   C. T0 = Q1 + X
   D. T0 = 1
   Answer: A. From the K-map T0 = Q0X' + Q0'X = Q0 XOR X, needing just one XOR gate. (Key point: T0 equation)

## Related in Digital Logic

- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 1101 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1110 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1110-t) — Digital Logic, chapter 9, asked 7×

## Related in other subjects

- [Sequence detector 1011 state diagram and VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-sequence-detector-1011) — Embedded System, chapter 9
- [FSM for binary serial addition](https://www.bctengineer.com/question.md?key=semester_4%2Fdiscrete_structure%3Afsm-binary-serial-addition) — Discrete Structure, chapter 2
- [Data logger input scanner and conditioner design](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adatalogger-three-transducers) — Instrumentation II, chapter 5
- [VHDL entity declaration; T flip-flops circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-two-tff-inverter) — Embedded System, chapter 9