---
title: "Sequence detector 110 using JK flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-110-jk"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-110-jk
site: BCT Engineering
---

# Sequence detector 110 using JK flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2081 Bhadra, 12 marks; 2080 Baisakh, 10 marks; 2074 Chaitra, 10 marks (asked 3 times)
- Video: [Design a sequence detector to detect 110 || Draw state diagram  for 110  sequence detector.](https://www.youtube.com/watch?v=yepMDN_siuU) — Sirisha Vamsi
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-110-jk
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a sequential machine that produces output Y = 1 when it detects the serial message X = 110 using JK flip-flop.

## Short answer

Mealy machine: states A=00 (idle), B=01 (got '1'), C=10 (got '11'). Equations: J1=Q0X, K1=X', J0=Q1'X, K0=1, Y=Q1X'. Output Y=1 when X=0 in state C, detecting 110 with overlapping sequences. Unused state 11 self-corrects.

## Answer

The machine has one serial input X and one output Y. Y = 1 when the last three bits received are 1, 1, 0.

A **Mealy** machine is used (output depends on the present state and the present input), and overlapping sequences are detected. Since the sequence has 3 bits, 3 states are needed, so **2 JK flip-flops** ($Q_1Q_0$) are used, clocked on the positive edge. (A Moore machine would need 4 states.)

#### Step 1: States
| Present state | Meaning | Next (X=0) | Next (X=1) | Y (X=0) | Y (X=1) |
|---|---|---|---|---|---|
| A | reset / no useful bits | A | B | 0 | 0 |
| B | "1" received | A | C | 0 | 0 |
| C | "11" received | A | C | 1 | 0 |

#### Step 2: State diagram
```text
 Main path (label = X/Y):
 A -1/0-> B -1/0-> C -0/1-> A
 Other transitions:
 A -0/0-> A    B -0/0-> A
 C -1/0-> C
```

#### Step 3: State assignment
| State | A | B | C |
|---|---|---|---|
| Q1 Q0 | 0 0 | 0 1 | 1 0 |

Code 11 is unused and is treated as a don't care.

#### Step 4: Excitation table
JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

| Q1 Q0 | X | Q1+ Q0+ | J1 | K1 | J0 | K0 | Y |
|---|---|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | X | 0 | X | 0 |
| 0 0 | 1 | 0 1 | 0 | X | 1 | X | 0 |
| 0 1 | 0 | 0 0 | 0 | X | X | 1 | 0 |
| 0 1 | 1 | 1 0 | 1 | X | X | 1 | 0 |
| 1 0 | 0 | 0 0 | X | 1 | 0 | X | 1 |
| 1 0 | 1 | 1 0 | X | 0 | 0 | X | 0 |

#### Step 5: K-maps (rows $Q_1$, columns $Q_0X$)
| J1: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 1 | X | X | X | X |

| K1: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | X | X |
| 1 | 1 | 0 | X | X |

| J0: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | X | X |
| 1 | 0 | 0 | X | X |

| K0: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | 1 | 1 |
| 1 | X | X | X | X |

| Y: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | X | X |

#### Step 6: Equations
$$
\begin{aligned} &J_1 = Q_0X,\quad K_1 = \overline{X} \\ &J_0 = \overline{Q_1}X,\quad K_0 = 1 \\ &Y = Q_1\overline{X} \end{aligned}
$$

#### Step 7: Logic diagram
```text
   +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1
   | FF0 |       | FF1 |
K0>|K    |    K1>|K    |
   +--^--+       +--^--+
      |             |
CLK---+-------------+
X = serial input, common to the gates
J1 = Q0.X   K1 = X'
J0 = Q1'.X   K0 = 1
Y = Q1.X'
```
The gates for each flip-flop input are built from the equations; the output gate gives Y directly (Mealy output).

**Unused state 11:** with the equations above, from 11 the machine goes to 00 when X = 0 and to 10 when X = 1, so it enters the valid states after one clock. Since Y can be 1 from state 11 for one clock, the flip-flops should be cleared to 00 at power-on (reset).

#### Check with an input stream
| X | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| State | A | A | B | C | A | B | C | C | A | B |
| Y | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |

Y = 1 appears exactly on the clock in which the last bit of 110 arrives; overlapping sequences are also detected.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why does the 110 detector need only 3 states and 2 flip-flops?
   A. Mealy output depends on present state and input, so states for 0, 1 and 11 bits received suffice
   B. Moore machines need fewer states
   C. The sequence has 3 bits so 3 flip-flops
   D. Each input needs a state
   Answer: A. Mealy outputs use the input on the last transition, so 3 states (A, B, C) suffice; Moore would need 4. (Key point: Mealy states)

2. In state C ('11' received), what happens when X = 1?
   A. Go to A, Y = 1
   B. Go to B
   C. Stay in C, Y = 0
   D. Go to A, Y = 0
   Answer: C. A further 1 still leaves the last two bits as 11, so it stays in C with Y = 0 (overlap). (Key point: State transitions)

3. What is the output equation and when is Y = 1?
   A. Y = Q1 X' (state C and X = 0)
   B. Y = Q1 X
   C. Y = Q0 X'
   D. Y = Q1' X
   Answer: A. Y = 1 only in state C (Q1Q0 = 10) when the final 0 arrives. (Key point: Output equation)

4. What happens from unused state 11 and why reset?
   A. It goes to 00 or 10 after one clock but Y may be 1 once, so reset at power-on
   B. It stays in 11 forever
   C. It goes to 01
   D. It is never reachable
   Answer: A. From 11 the machine reaches valid states after one clock, but Y = Q1X' can briefly be 1, so a reset is advised. (Key point: Unused state)

## Related in Digital Logic

- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 1101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1110 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1110-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 110 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-sr-msb) — Digital Logic, chapter 9

## Related in other subjects

- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6
- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9