--- title: "Sequence detector 110 using SR flip-flops" subject: "Digital Logic" chapter: 9 key: "semester_3/digital_logic:detector-110-sr-msb" source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-110-sr-msb site: BCT Engineering --- # Sequence detector 110 using SR flip-flops Digital Logic · Chapter 9: Sequential Machines - Asked in: 2068 Baisakh, 12 marks - Video: [Sequence or Pattern Detector](https://www.youtube.com/watch?v=XNAK-L7NlOM) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-110-sr-msb - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9 ## Question Design a synchronous state machine with the following specification: a) No. of input: 1 b) No. of output: 1 c) The output of the machine is to be set high when the data in the input is 110 in sequence, starting from the MSB (Use SR flip-flop). ## Short answer Mealy machine, input MSB first: states A (reset), B (1 received), C (11 received). SR flip-flops, assignment A=00, B=01, C=10. Equations: S1 = Q0 X, R1 = X', S0 = Q1' Q0' X, R0 = Q0. Output Z = Q1 X'. ## Answer "Starting from the MSB" means the bits arrive serially in the order 1, 1, 0 (MSB first). A **Mealy** machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of **110** arrives. Flip-flops: **S-R**. States (what has been received so far): - **A**: reset / last bit 0 - **B**: "1" (first bit, MSB) received - **C**: "11" received #### State diagram (Mealy) ```text Arc label = input/output A --1/0--> B --1/0--> C --0/1--> A A --0/0--> A (self loop) B --0/0--> A C --1/0--> C (self loop) ``` #### State table | Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) | |---|---|---|---|---| | A | A | B | 0 | 0 | | B | A | C | 0 | 0 | | C | A | C | 1 | 0 | #### State assignment A = 00, B = 01, C = 10 (flip-flop outputs $Q_1 Q_0$). The unused code 11 is taken as don't care (x) in all K-maps. The flip-flops are cleared to 00 at power-on (start state). Checking the final equations, from 11 the machine goes to a valid state on the next clock (X=0 goes to A, X=1 goes to C), so it is self-starting. #### Excitation table of S-R flip-flop | Q | Q+ | S | R | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | x | 0 | #### Transition and excitation table | Q1 Q0 | X | Q1+ Q0+ | S1 | R1 | S0 | R0 | Z | |---|---|---|---|---|---|---|---| | 0 0 | 0 | 0 0 | 0 | x | 0 | x | 0 | | 0 0 | 1 | 0 1 | 0 | x | 1 | 0 | 0 | | 0 1 | 0 | 0 0 | 0 | x | 0 | 1 | 0 | | 0 1 | 1 | 1 0 | 1 | 0 | 0 | 1 | 0 | | 1 0 | 0 | 0 0 | 0 | 1 | 0 | x | 1 | | 1 0 | 1 | 1 0 | x | 0 | 0 | x | 0 | #### K-maps and simplified equations ```text S1 X=0 X=1 Q1Q0=00 0 0 Q1Q0=01 0 1 Q1Q0=11 x x Q1Q0=10 0 x R1 X=0 X=1 Q1Q0=00 x x Q1Q0=01 x 0 Q1Q0=11 x x Q1Q0=10 1 0 S0 X=0 X=1 Q1Q0=00 0 1 Q1Q0=01 0 0 Q1Q0=11 x x Q1Q0=10 0 0 R0 X=0 X=1 Q1Q0=00 x 0 Q1Q0=01 1 1 Q1Q0=11 x x Q1Q0=10 x x Z X=0 X=1 Q1Q0=00 0 0 Q1Q0=01 0 0 Q1Q0=11 x x Q1Q0=10 1 0 ``` $$ \begin{aligned} S_1 &= Q_0 X \\ R_1 &= X' \\ S_0 &= Q_1' Q_0' X \\ R_0 &= Q_0 \\ Z &= Q_1 X' \end{aligned} $$ #### Logic diagram ```text +-------------+ +----------+ X ------>| next-state |---->| FF1, FF0 |--+--> Q1, Q0 +----->| logic | | (CLK) | | | +-------------+ +----------+ | +-------------------<--------------------+ | +-------------+ +----->| output |----> Z X ------>| logic | +-------------+ ``` Gates needed (two S-R flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates): - $S_1$: a 2-input AND for $Q_0 X$. - $R_1$: direct line $X'$. - $S_0$: a 3-input AND for $Q_1' Q_0' X$. - $R_0$: direct line $Q_0$. - $Z$: a 2-input AND for $Q_1 X'$. **Check:** input X = 0110110 gives Z = 0001001; Z = 1 at bits 4 and 7. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does 'starting from the MSB' mean here? A. Bits arrive in the order 1, 1, 0 B. Bits arrive in the order 0, 1, 1 C. The output is taken from the MSB flip-flop D. The machine is cleared to 11 Answer: A. MSB first means the first bit received is the most significant, so the stream 110 arrives as 1, 1, 0. (Key point: MSB first) 2. Which S-R inputs are needed for a flip-flop that must go from 1 to 0? A. S = 1, R = 0 B. S = 0, R = 1 C. S = x, R = 0 D. S = 1, R = 1 Answer: B. To reset a flip-flop from 1 to 0, S = 0 and R = 1. (Key point: S-R excitation) 3. Which equation gives S0 (set of the Q0 flip-flop) for this detector? A. S0 = Q0 X B. S0 = Q1 X' C. S0 = Q1' Q0' X D. S0 = Q0 Answer: C. Q0 must go 0 to 1 only from A (00) when X = 1, giving S0 = Q1' Q0' X. (Key point: Equation) 4. How does the design handle the unused code 11? A. It is the reset state B. It is forced to output Z = 1 C. It is ignored and may lock up D. It is taken as don't care and goes to a valid state on the next clock Answer: D. 11 is a don't care in the K-maps; the final equations send it to A (X=0) or C (X=1), so the circuit is self-starting. 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