---
title: "Sequence detector 1101 using SR flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-1101-sr"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1101-sr
site: BCT Engineering
---

# Sequence detector 1101 using SR flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2081 Bhadra, 12 marks; 2076 Asoj (asked 2 times)
- Video: [Sequence Detector (Example)](https://www.youtube.com/watch?v=HXG_YPVNIsM) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1101-sr
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a sequential machine that consists of a single input, X and the single output, Z. The machine is required to give output high when input contains serial message 1101 sequence. Use SR flip-flops only.

## Short answer

Use a Mealy machine with overlap and 2 SR flip-flops. Encode the four states as A=00, B=01, C=10, D=11. The flip-flop equations are S1 = Q1' Q0 X, R1 = Q1 Q0; S0 = Q1 Q0' X' + Q1' Q0' X, R0 = Q1' Q0 + Q0 X'; output Z = Q1 Q0 X.

## Answer

The machine has one serial input X and one output Z. Z = 1 when the last four bits received are 1, 1, 0, 1. Only SR flip-flops are used.

A **Mealy** machine is used (output depends on the present state and the present input), and overlapping sequences are detected. Since the sequence has 4 bits, 4 states are needed, so **2 SR flip-flops** ($Q_1Q_0$) are used, clocked on the positive edge. (A Moore machine would need 5 states.)

#### Step 1: States
| Present state | Meaning | Next (X=0) | Next (X=1) | Z (X=0) | Z (X=1) |
|---|---|---|---|---|---|
| A | reset / no useful bits | A | B | 0 | 0 |
| B | "1" received | A | C | 0 | 0 |
| C | "11" received | D | C | 0 | 0 |
| D | "110" received | A | B | 0 | 1 |

#### Step 2: State diagram
```text
 Main path (label = X/Z):
 A -1/0-> B -1/0-> C -0/0-> D -1/1-> B
 Other transitions:
 A -0/0-> A    B -0/0-> A
 C -1/0-> C    D -0/0-> A
```

#### Step 3: State assignment
| State | A | B | C | D |
|---|---|---|---|---|
| Q1 Q0 | 0 0 | 0 1 | 1 0 | 1 1 |

#### Step 4: Excitation table
SR excitation: 0→0: S=0, R=X; 0→1: S=1, R=0; 1→0: S=0, R=1; 1→1: S=X, R=0.

| Q1 Q0 | X | Q1+ Q0+ | S1 | R1 | S0 | R0 | Z |
|---|---|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | X | 0 | X | 0 |
| 0 0 | 1 | 0 1 | 0 | X | 1 | 0 | 0 |
| 0 1 | 0 | 0 0 | 0 | X | 0 | 1 | 0 |
| 0 1 | 1 | 1 0 | 1 | 0 | 0 | 1 | 0 |
| 1 0 | 0 | 1 1 | X | 0 | 1 | 0 | 0 |
| 1 0 | 1 | 1 0 | X | 0 | 0 | X | 0 |
| 1 1 | 0 | 0 0 | 0 | 1 | 0 | 1 | 0 |
| 1 1 | 1 | 0 1 | 0 | 1 | X | 0 | 1 |

#### Step 5: K-maps (rows $Q_1$, columns $Q_0X$)
| S1: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 1 | X | X | 0 | 0 |

| R1: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | 0 | X |
| 1 | 0 | 0 | 1 | 1 |

| S0: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | X | 0 |

| R0: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | 0 | 1 | 1 |
| 1 | 0 | X | 0 | 1 |

| Z: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |

#### Step 6: Equations
$$
\begin{aligned} &S_1 = \overline{Q_1}Q_0X,\quad R_1 = Q_1Q_0 \\ &S_0 = Q_1\overline{Q_0}\overline{X} + \overline{Q_1}\overline{Q_0}X,\quad R_0 = \overline{Q_1}Q_0 + Q_0\overline{X} \\ &Z = Q_1Q_0X \end{aligned}
$$

#### Step 7: Logic diagram
```text
   +-----+       +-----+
S0>|S   Q|-Q0 S1>|S   Q|-Q1
   | FF0 |       | FF1 |
R0>|R    |    R1>|R    |
   +--^--+       +--^--+
      |             |
CLK---+-------------+
X = serial input, common to the gates
S1 = Q1'.Q0.X   R1 = Q1.Q0
S0 = Q1.Q0'.X' + Q1'.Q0'.X   R0 = Q1'.Q0 + Q0.X'
Z = Q1.Q0.X
```
The gates for each flip-flop input are built from the equations; the output gate gives Z directly (Mealy output).

#### Check with an input stream
| X | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| State | A | A | B | C | D | B | C | D | B | A |
| Z | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |

Z = 1 appears exactly on the clock in which the last bit of 1101 arrives; overlapping sequences are also detected.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why does the Mealy 1101 detector use 4 states and 2 flip-flops?
   A. Each of the 4 bits needs a flip-flop
   B. States remember 0, 1, 11 and 110 bits received
   C. Moore needs 4 and Mealy needs 5
   D. Because SR flip-flops come in pairs
   Answer: B. The states are A (none), B (1), C (11), D (110); Mealy gives Z on the last bit, so 4 states. (Key point: Number of states)

2. In state D ('110' received), what happens when X = 1?
   A. Go to A with Z = 0
   B. Go to C with Z = 1
   C. Go to B with Z = 1
   D. Stay in D
   Answer: C. Last bit 1 completes 1101, Z = 1, and the final 1 can start a new sequence so it goes to B. (Key point: State D on input 1)

3. In state C ('11'), what happens on X = 0?
   A. Go to D
   B. Go to A
   C. Go to B
   D. Stay in C
   Answer: A. The last three bits are now 110, which is state D. (Key point: Handling a 0 in state C)

4. What S, R inputs are needed for 0 -> 0?
   A. S = 1, R = 0
   B. S = 0, R = X
   C. S = X, R = 1
   D. S = 1, R = 1
   Answer: B. To stay at 0, S must be 0 and R is a don't care. (Key point: SR excitation for Q 0->0)

## Close variants set in other exams

- [Sequence detector 1101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1110 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1110-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1001 using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-d) — Digital Logic, chapter 9, asked 9×

## Related in Digital Logic

- [Sequence detector 1001 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 110 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-sr-msb) — Digital Logic, chapter 9
- [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×
- [Sequence detector 1010 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1010-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-101-t) — Digital Logic, chapter 9
- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×

## Related in other subjects

- [Sequence detector 1101 FSM and VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-sequence-detector-1101) — Embedded System, chapter 9