---
title: "Sequence detector 1101 using T flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-1101-t"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1101-t
site: BCT Engineering
---

# Sequence detector 1101 using T flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2081 Baisakh, 12 marks
- Video: [Sequence detector 1100 || sequence detector 1101 overlapping mealy FSM](https://www.youtube.com/watch?v=SZhgyuQgjZ8) — VLSI-LEARNINGS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1101-t
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a sequential machine that has a single input 'x' and single output 'y'. The machine is required to give high output (y=1) when it detects the serial sequence of x = 1101 message. Use T flip-flops only.

## Short answer

Mealy machine with 2 T flip-flops; states A(00), B(01), C(10), D(11). T1 = Q1Q0 + Q0x, T0 = Q1x' + Q1'x + Q0x', y = Q1Q0x. Overlapping sequences detected.

## Answer

The machine has a single input x and a single output y; y = 1 when the last four bits received are 1, 1, 0, 1. Only T flip-flops are used.

A **Mealy** machine is used (output depends on the present state and the present input), and overlapping sequences are detected. Since the sequence has 4 bits, 4 states are needed, so **2 T flip-flops** ($Q_1Q_0$) are used, clocked on the positive edge. (A Moore machine would need 5 states.)

#### Step 1: States
| Present state | Meaning | Next (x=0) | Next (x=1) | y (x=0) | y (x=1) |
|---|---|---|---|---|---|
| A | reset / no useful bits | A | B | 0 | 0 |
| B | "1" received | A | C | 0 | 0 |
| C | "11" received | D | C | 0 | 0 |
| D | "110" received | A | B | 0 | 1 |

#### Step 2: State diagram
```text
 Main path (label = x/y):
 A -1/0-> B -1/0-> C -0/0-> D -1/1-> B
 Other transitions:
 A -0/0-> A    B -0/0-> A
 C -1/0-> C    D -0/0-> A
```

#### Step 3: State assignment
| State | A | B | C | D |
|---|---|---|---|---|
| Q1 Q0 | 0 0 | 0 1 | 1 0 | 1 1 |

#### Step 4: Excitation table
T excitation: T = 1 when the flip-flop must change, T = 0 when it must hold ($T = Q \oplus Q^+$).

| Q1 Q0 | x | Q1+ Q0+ | T1 | T0 | y |
|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | 0 | 0 |
| 0 0 | 1 | 0 1 | 0 | 1 | 0 |
| 0 1 | 0 | 0 0 | 0 | 1 | 0 |
| 0 1 | 1 | 1 0 | 1 | 1 | 0 |
| 1 0 | 0 | 1 1 | 0 | 1 | 0 |
| 1 0 | 1 | 1 0 | 0 | 0 | 0 |
| 1 1 | 0 | 0 0 | 1 | 1 | 0 |
| 1 1 | 1 | 0 1 | 1 | 0 | 1 |

#### Step 5: K-maps (rows $Q_1$, columns $Q_0x$)
| T1: Q1 / Q0x | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 |

| T0: Q1 / Q0x | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 1 |

| y: Q1 / Q0x | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |

#### Step 6: Equations
$$
\begin{aligned} &T_1 = Q_1Q_0 + Q_0x \\ &T_0 = Q_1\overline{x} + \overline{Q_1}x + Q_0\overline{x} \\ &y = Q_1Q_0x \end{aligned}
$$

#### Step 7: Logic diagram
```text
   +-----+       +-----+
T0>|T   Q|-Q0 T1>|T   Q|-Q1
   | FF0 |       | FF1 |
   |     |       |     |
   +--^--+       +--^--+
      |             |
CLK---+-------------+
x = serial input, common to the gates
T1 = Q1.Q0 + Q0.x
T0 = Q1.x' + Q1'.x + Q0.x'
y = Q1.Q0.x
```
The gates for each flip-flop input are built from the equations; the output gate gives y directly (Mealy output).

#### Check with an input stream
| x | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| State | A | B | C | D | B | C | D | B | C | D |
| y | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |

y = 1 appears exactly on the clock in which the last bit of 1101 arrives; overlapping sequences are also detected.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. For a T flip-flop, when must T = 1?
   A. When the next state is 1
   B. When the present state is 1
   C. When the flip-flop must change its state (T = Q xor Q+)
   D. When the flip-flop must hold its state
   Answer: C. A T flip-flop toggles when T = 1, so T = Q xor Q+: 1 for a change, 0 for a hold. (Key point: T excitation)

2. In state C ("11" received), what happens on x = 1?
   A. Go to D
   B. Stay in C, because 111 still ends in 11
   C. Go to B
   D. Go to A
   Answer: B. After 111 the last two bits are still 11, so the machine stays in C. (Key point: State C behaviour)

3. In state D ("110") with x = 1, what are y and the next state?
   A. y = 1, next state B (the last 1 may start a new 1101)
   B. y = 1, next state A
   C. y = 0, next state B
   D. y = 0, next state C
   Answer: A. 110 plus 1 completes 1101, so y = 1. The final 1 is a useful tail, so the next state is B. (Key point: Detection and overlap)

4. What is the output equation?
   A. y = Q1 Q0' x
   B. y = Q1' Q0 x
   C. y = Q1 Q0 x'
   D. y = Q1 Q0 x
   Answer: D. y = 1 only in state D (Q1Q0 = 11) when x = 1. (Key point: Output equation)

## Close variants set in other exams

- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1110 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1110-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1101 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1001 using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-d) — Digital Logic, chapter 9, asked 9×

## Related in Digital Logic

- [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×
- [Sequence detector 1010 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1010-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1001 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-101-t) — Digital Logic, chapter 9
- [Sequence detector 110 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×

## Related in other subjects

- [Sequence detector 1101 FSM and VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-sequence-detector-1101) — Embedded System, chapter 9