---
title: "Sequence detector 1110 using T flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-1110-t"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1110-t
site: BCT Engineering
---

# Sequence detector 1110 using T flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2082 Baisakh, 10 marks
- Video: [sequence detector 1110 || sequence detector 1111 overlapping mealy FSM](https://www.youtube.com/watch?v=GjwzeSjF9LU) — VLSI-LEARNINGS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1110-t
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a sequential machine that has a single input 'X' and single output 'Z'. The machine is required to give high output when it detects the serial sequence of 1110 message. Use T-flip-flops only.

## Short answer

Four states: A(00), B(01), C(10), D(11). T flip-flop inputs: T1 = Q1 X' + Q1' Q0 X, T0 = Q0 X' + Q0' X + Q1' X, output Z = Q1 Q0 X'.

## Answer

A **Mealy** machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of **1110** arrives. Flip-flops: **T**.

States (what has been received so far):

- **A**: reset / last bit 0
- **B**: "1" received
- **C**: "11" received
- **D**: "111" received (stays in D on more 1s)

#### State diagram (Mealy)

```text
Arc label = input/output

 A --1/0--> B --1/0--> C --1/0--> D --0/1--> A

 A --0/0--> A  (self loop)
 B --0/0--> A
 C --0/0--> A
 D --1/0--> D  (self loop)
```

#### State table

| Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) |
|---|---|---|---|---|
| A | A | B | 0 | 0 |
| B | A | C | 0 | 0 |
| C | A | D | 0 | 0 |
| D | A | D | 1 | 0 |

#### State assignment

A = 00, B = 01, C = 10, D = 11 (flip-flop outputs $Q_1 Q_0$). 

#### Excitation table of T flip-flop

| Q | Q+ | T |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |

#### Transition and excitation table

| Q1 Q0 | X | Q1+ Q0+ | T1 | T0 | Z |
|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | 0 | 0 |
| 0 0 | 1 | 0 1 | 0 | 1 | 0 |
| 0 1 | 0 | 0 0 | 0 | 1 | 0 |
| 0 1 | 1 | 1 0 | 1 | 1 | 0 |
| 1 0 | 0 | 0 0 | 1 | 0 | 0 |
| 1 0 | 1 | 1 1 | 0 | 1 | 0 |
| 1 1 | 0 | 0 0 | 1 | 1 | 1 |
| 1 1 | 1 | 1 1 | 0 | 0 | 0 |

#### K-maps and simplified equations

```text
T1          X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    1
Q1Q0=11       1    0
Q1Q0=10       1    0

T0          X=0  X=1
Q1Q0=00       0    1
Q1Q0=01       1    1
Q1Q0=11       1    0
Q1Q0=10       0    1

Z           X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    0
Q1Q0=11       1    0
Q1Q0=10       0    0
```

$$
\begin{aligned} T_1 &= Q_1 X' + Q_1' Q_0 X \\ T_0 &= Q_0 X' + Q_0' X + Q_1' X \\ Z &= Q_1 Q_0 X' \end{aligned}
$$

#### Logic diagram

```text
           +-------------+     +----------+
 X  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> Z
 X  ------>| logic       |
           +-------------+
```

Gates needed (two T flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates):

- $T_1$: a 2-input AND for $Q_1 X'$; a 3-input AND for $Q_1' Q_0 X$, combined in a 2-input OR gate.
- $T_0$: a 2-input AND for $Q_0 X'$; a 2-input AND for $Q_0' X$; a 2-input AND for $Q_1' X$, combined in a 3-input OR gate.
- $Z$: a 3-input AND for $Q_1 Q_0 X'$.

**Check:** input X = 0111101110 gives Z = 0000010001; Z = 1 at bits 6 and 10. Note D stays in D on 1, since "1111" still ends in "111".

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why does state D stay in D on X=1?
   A. Because 1111 still ends in 111
   B. Because D is the reset state
   C. Because overlap is not allowed
   D. Because Z must remain 1
   Answer: A. Any number of 1s still leaves 111 as the last three bits, so the machine stays in D. (Key point: State D)

2. How is T found for a T flip-flop?
   A. T = Q' Q+
   B. T = Q xor Q+ (1 whenever the flip-flop must change)
   C. T = Q+
   D. T = Q and Q+
   Answer: B. T = 1 exactly when the flip-flop must toggle, so T = Q xor Q+. (Key point: T excitation)

3. Why are no don't cares used in this design?
   A. T flip-flops cannot use don't cares
   B. The unused states are all reset
   C. Four states use all four codes 00 to 11
   D. Z is always 1
   Answer: C. With A to D coded 00 to 11 every code is used, so no unused codes exist. (Key point: State assignment)

4. Which output equation was found?
   A. Z = Q1 Q0 X
   B. Z = Q1 X'
   C. Z = Q0' X
   D. Z = Q1 Q0 X'
   Answer: D. Z = 1 only in state D (11) when X = 0, i.e. Z = Q1 Q0 X'. (Key point: Output)

## Close variants set in other exams

- [Sequence detector 1101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1101 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1001 using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-d) — Digital Logic, chapter 9, asked 9×

## Related in Digital Logic

- [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×
- [Sequence detector 1010 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1010-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1001 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-101-t) — Digital Logic, chapter 9
- [Sequence detector 110 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×