--- title: "Detector for three consecutive zeros" subject: "Digital Logic" chapter: 9 key: "semester_3/digital_logic:detector-three-zeros" source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-three-zeros site: BCT Engineering --- # Detector for three consecutive zeros Digital Logic · Chapter 9: Sequential Machines - Asked in: 2069 Chaitra, 12 marks - Video: [How to Design a sequential Circuit that Detects Three or More Consecutive 1's in the Input String?](https://www.youtube.com/watch?v=DSClog6vn3A) — EE-Vibes (Electrical Engineering Lessons) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-three-zeros - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9 ## Question Design a sequential machine that detects three consecutive zeros from an input data stream X by making output, Y = 1. ## Short answer Mealy machine detecting three consecutive zeros with states A (reset/last bit 1), B (one zero), C (two or more zeros). JK flip-flops, assignment A=00, B=01, C=10. Equations: J1 = Q0 X', K1 = X, J0 = Q1' X', K0 = 1, Z = Q1 X'. ## Answer No flip-flop type is specified, so J-K flip-flops are used. Output Y of the question is written Z (Y = Z). With overlapping, a run of four 0s gives Y = 1 on the 3rd and 4th zero. A **Mealy** machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of **000** arrives. Flip-flops: **J-K**. States (what has been received so far): - **A**: reset / last bit 1 - **B**: one 0 received - **C**: two or more consecutive 0s received #### State diagram (Mealy) ```text Arc label = input/output A --0/0--> B --0/0--> C --0/1--> C A --1/0--> A (self loop) B --1/0--> A C --1/0--> A ``` #### State table | Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) | |---|---|---|---|---| | A | B | A | 0 | 0 | | B | C | A | 0 | 0 | | C | C | A | 1 | 0 | #### State assignment A = 00, B = 01, C = 10 (flip-flop outputs $Q_1 Q_0$). The unused code 11 is taken as don't care (x) in all K-maps. The flip-flops are cleared to 00 at power-on (start state). Checking the final equations, from 11 the machine goes to a valid state on the next clock (X=0 goes to C, X=1 goes to A), so it is self-starting. #### Excitation table of J-K flip-flop | Q | Q+ | J | K | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | x | | 1 | 0 | x | 1 | | 1 | 1 | x | 0 | #### Transition and excitation table | Q1 Q0 | X | Q1+ Q0+ | J1 | K1 | J0 | K0 | Z | |---|---|---|---|---|---|---|---| | 0 0 | 0 | 0 1 | 0 | x | 1 | x | 0 | | 0 0 | 1 | 0 0 | 0 | x | 0 | x | 0 | | 0 1 | 0 | 1 0 | 1 | x | x | 1 | 0 | | 0 1 | 1 | 0 0 | 0 | x | x | 1 | 0 | | 1 0 | 0 | 1 0 | x | 0 | 0 | x | 1 | | 1 0 | 1 | 0 0 | x | 1 | 0 | x | 0 | #### K-maps and simplified equations ```text J1 X=0 X=1 Q1Q0=00 0 0 Q1Q0=01 1 0 Q1Q0=11 x x Q1Q0=10 x x K1 X=0 X=1 Q1Q0=00 x x Q1Q0=01 x x Q1Q0=11 x x Q1Q0=10 0 1 J0 X=0 X=1 Q1Q0=00 1 0 Q1Q0=01 x x Q1Q0=11 x x Q1Q0=10 0 0 K0 X=0 X=1 Q1Q0=00 x x Q1Q0=01 1 1 Q1Q0=11 x x Q1Q0=10 x x Z X=0 X=1 Q1Q0=00 0 0 Q1Q0=01 0 0 Q1Q0=11 x x Q1Q0=10 1 0 ``` $$ \begin{aligned} J_1 &= Q_0 X' \\ K_1 &= X \\ J_0 &= Q_1' X' \\ K_0 &= 1 \\ Z &= Q_1 X' \end{aligned} $$ #### Logic diagram ```text +-------------+ +----------+ X ------>| next-state |---->| FF1, FF0 |--+--> Q1, Q0 +----->| logic | | (CLK) | | | +-------------+ +----------+ | +-------------------<--------------------+ | +-------------+ +----->| output |----> Z X ------>| logic | +-------------+ ``` Gates needed (two J-K flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates): - $J_1$: a 2-input AND for $Q_0 X'$. - $K_1$: direct line $X$. - $J_0$: a 2-input AND for $Q_1' X'$. - $K_0$: tied to logic 1. - $Z$: a 2-input AND for $Q_1 X'$. **Check:** input X = 1000010 gives Z = 0001100; Z = 1 at the 4th and 5th bits (third and fourth consecutive 0). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. With overlapping allowed, what is Y for input 0000? A. Y = 1 on the 3rd and 4th zeros B. Y = 1 only on the 3rd zero C. Y = 1 only on the 4th zero D. Y stays 0 until a 1 arrives Answer: A. State C stays in C on 0 with output 1, so every 0 after two 0s gives Y = 1. (Key point: Overlapping) 2. What does state C represent? A. Exactly three zeros received B. Two or more consecutive 0s received C. A 1 was just received D. The reset state Answer: B. C is reached after two 0s and stays on further 0s, so it means two or more consecutive zeros. (Key point: State C) 3. Which are the J-K input equations obtained? A. J1 = Q0 X, K1 = X', J0 = Q1' X, K0 = 1 B. J1 = Q0 X', K1 = X', J0 = Q1 X', K0 = 0 C. J1 = Q0 X', K1 = X, J0 = Q1' X', K0 = 1 D. J1 = X, K1 = Q0, J0 = X', K0 = 0 Answer: C. From the excitation table: J1 = Q0 X', K1 = X, J0 = Q1' X', K0 = 1. (Key point: J-K equations) 4. Which output equation gives Y = 1 for 000? A. Z = Q0 X' B. Z = Q1 X C. Z = Q1' Q0' X' D. Z = Q1 X' Answer: D. Z = 1 only in state C (10) with X = 0, which simplifies to Q1 X' using 11 as don't care. (Key point: Output) ## Close variants set in other exams - [Three consecutive zeros detector using SR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-three-zeros-sr) — Digital Logic, chapter 9, asked 2× ## Related in Digital Logic - [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×