--- title: "Three consecutive zeros detector using SR" subject: "Digital Logic" chapter: 9 key: "semester_3/digital_logic:detector-three-zeros-sr" source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-three-zeros-sr site: BCT Engineering --- # Three consecutive zeros detector using SR Digital Logic · Chapter 9: Sequential Machines - Asked in: 2078 Kartik, 10 marks - Video: [Sequence Detector (Example)](https://www.youtube.com/watch?v=HXG_YPVNIsM) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-three-zeros-sr - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9 ## Question Design a sequential machine that detects three consecutive zeros from an input data stream x by making output y=1. (Use SR flip flop in your design) ## Short answer A Mealy machine with states A(00), B(01), C(10) detects overlapping '000'. S-R flip-flop excitation yields S1 = Q0 X', R1 = X, S0 = Q1' Q0' X', R0 = Q0, output Z = Q1 X'. ## Answer Output y of the question is written Z (y = Z). With overlapping, every 0 after two 0s gives Z = 1. A **Mealy** machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of **000** arrives. Flip-flops: **S-R**. States (what has been received so far): - **A**: reset / last bit 1 - **B**: one 0 received - **C**: two or more consecutive 0s #### State diagram (Mealy) ```text Arc label = input/output A --0/0--> B --0/0--> C --0/1--> C A --1/0--> A (self loop) B --1/0--> A C --1/0--> A ``` #### State table | Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) | |---|---|---|---|---| | A | B | A | 0 | 0 | | B | C | A | 0 | 0 | | C | C | A | 1 | 0 | #### State assignment A = 00, B = 01, C = 10 (flip-flop outputs $Q_1 Q_0$). The unused code 11 is taken as don't care (x) in all K-maps. The flip-flops are cleared to 00 at power-on (start state). Checking the final equations, from 11 the machine goes to a valid state on the next clock (X=0 goes to C, X=1 goes to A), so it is self-starting. #### Excitation table of S-R flip-flop | Q | Q+ | S | R | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | x | 0 | #### Transition and excitation table | Q1 Q0 | X | Q1+ Q0+ | S1 | R1 | S0 | R0 | Z | |---|---|---|---|---|---|---|---| | 0 0 | 0 | 0 1 | 0 | x | 1 | 0 | 0 | | 0 0 | 1 | 0 0 | 0 | x | 0 | x | 0 | | 0 1 | 0 | 1 0 | 1 | 0 | 0 | 1 | 0 | | 0 1 | 1 | 0 0 | 0 | x | 0 | 1 | 0 | | 1 0 | 0 | 1 0 | x | 0 | 0 | x | 1 | | 1 0 | 1 | 0 0 | 0 | 1 | 0 | x | 0 | #### K-maps and simplified equations ```text S1 X=0 X=1 Q1Q0=00 0 0 Q1Q0=01 1 0 Q1Q0=11 x x Q1Q0=10 x 0 R1 X=0 X=1 Q1Q0=00 x x Q1Q0=01 0 x Q1Q0=11 x x Q1Q0=10 0 1 S0 X=0 X=1 Q1Q0=00 1 0 Q1Q0=01 0 0 Q1Q0=11 x x Q1Q0=10 0 0 R0 X=0 X=1 Q1Q0=00 0 x Q1Q0=01 1 1 Q1Q0=11 x x Q1Q0=10 x x Z X=0 X=1 Q1Q0=00 0 0 Q1Q0=01 0 0 Q1Q0=11 x x Q1Q0=10 1 0 ``` $$ \begin{aligned} S_1 &= Q_0 X' \\ R_1 &= X \\ S_0 &= Q_1' Q_0' X' \\ R_0 &= Q_0 \\ Z &= Q_1 X' \end{aligned} $$ #### Logic diagram ```text +-------------+ +----------+ X ------>| next-state |---->| FF1, FF0 |--+--> Q1, Q0 +----->| logic | | (CLK) | | | +-------------+ +----------+ | +-------------------<--------------------+ | +-------------+ +----->| output |----> Z X ------>| logic | +-------------+ ``` Gates needed (two S-R flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates): - $S_1$: a 2-input AND for $Q_0 X'$. - $R_1$: direct line $X$. - $S_0$: a 3-input AND for $Q_1' Q_0' X'$. - $R_0$: direct line $Q_0$. - $Z$: a 2-input AND for $Q_1 X'$. **Check:** input X = 1000010 gives Z = 0001100; Z = 1 at bits 4 and 5. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. With overlapping, when is Z = 1? A. Every 0 after two 0s B. Only the third 0 C. Every 1 after three 0s D. Only after reset Answer: A. State C stays on 0 with output 1, so each further 0 gives Z = 1. (Key point: Overlap) 2. Which S and R values are needed in state C (10) when X=1 (next state 00) for Q1? A. S1 = 1, R1 = 0 B. S1 = 0, R1 = 1 C. S1 = x, R1 = 0 D. S1 = 0, R1 = 0 Answer: B. Q1 goes 1 to 0, so S1 = 0, R1 = 1. (Key point: S-R values) 3. Which equation gives S0? A. S0 = Q0 X' B. S0 = Q1 X C. S0 = Q1' Q0' X' D. S0 = X Answer: C. Q0 sets only from A when X = 0. (Key point: Equation) 4. Which output equation was found? A. Z = Q1 X B. Z = Q0 X' C. Z = Q1' X' D. Z = Q1 X' Answer: D. Z = 1 only in state C with X=0. (Key point: Output) ## Close variants set in other exams - [Detector for three consecutive zeros](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-three-zeros) — Digital Logic, chapter 9, asked 2× ## Related in Digital Logic - [Flip-flop as state machine; SR to JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aflipflop-state-machine-sr-to-jk) — Digital Logic, chapter 6 - [Sequence detector 110 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-sr-msb) — Digital Logic, chapter 9 - [Sequence detector 1101 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-sr) — Digital Logic, chapter 9, asked 7× - [Sequence detector 1001 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-sr) — Digital Logic, chapter 9, asked 7× - [Sequence detector 101 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-101-jk) — Digital Logic, chapter 9, asked 2× - [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2× ## Related in other subjects - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6×