--- title: "12-hour digital clock" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:digital-clock-12hr" source: https://www.bctengineer.com/q/semester_3/digital_logic/digital-clock-12hr site: BCT Engineering --- # 12-hour digital clock Digital Logic · Chapter 8: Counters - Asked in: 2076 Asoj - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/digital-clock-12hr - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Design 12-Hr. digital clock. ## Short answer A 12-hour digital clock uses mod-60 seconds and minutes counters. The hours counter has a mod-10 units and a single toggle flip-flop for tens. After 12, the next pulse gives 13; a NAND gate detecting T·U1·U0=1 clears the tens flip-flop and resets units to 0001 (01). BCD outputs drive 7447 decoders and displays. ## Answer A **12-hour digital clock** shows time from 01:00:00 to 12:59:59 (often with an AM/PM indicator). The seconds and minutes sections are mod-60 counters; the special part is the hours counter, which must count 01 → 12 and then return to **01** (not 00). #### Overall block diagram ```text AC 50 Hz -> [Shaper] -> [÷10] -> [÷5] -> 1 Hz | +--------------------------------------+ v SECONDS (00-59) [÷10 units] -----> [÷6 tens] -------+ 1 pulse/min | | | [7447 dec] [7447 dec] | [7-seg disp] [7-seg disp] | +---------------------------------+ v MINUTES (00-59) [÷10 units] -----> [÷6 tens] -------+ 1 pulse/h | | | [7447 dec] [7447 dec] | [7-seg disp] [7-seg disp] | +---------------------------------+ v HOURS (01-12) [÷10 units] -----> [tens FF] <--- reset/load logic | | [7447 dec] [decoder] [7-seg disp] [7-seg disp] ``` #### Seconds and minutes (÷60 each) - A 1 Hz signal is obtained from 50 Hz mains by a Schmitt trigger and a ÷50 divider (÷10, ÷5). - Units: mod-10 counter (0–9). Its $Q_3$ falling edge (9 → 0) clocks the tens counter. - Tens: mod-6 counter (0–5), cleared at 6 (0110) by a NAND of $Q_2$, $Q_1$. Its reset gives 1 pulse per minute (from seconds) or 1 pulse per hour (from minutes). #### Hours counter (01 to 12) - **Units:** mod-10 counter with outputs $U_3U_2U_1U_0$. - **Tens:** a single JK flip-flop (J = K = 1) with output T, clocked by $U_3$ when units go 9 → 0. So 09 → 10. - **Recycle logic:** after 12 the next pulse gives **13** (T = 1, units 0011). With T = 1 the units only reach 0, 1, 2, 3, so 13 is the first state with $T = U_1 = U_0 = 1$. A 3-input NAND gate detects it: $$ \overline{LOAD} = \overline{T\,U_1\,U_0} $$ Its low output clears the tens flip-flop and units bits $U_3, U_2, U_1$, and presets $U_0$, so the display jumps from 13 straight to **01**. ```text 1 pulse/h (from minutes section) | v +-----------+ U3 (9->0) +---------+ | Hours |------------>| Tens FF | T | units | | (J=K=1) | | MOD-10 | +---------+ +-----------+ | U3 U2 U1 U0 | | | | U1--+ +--U0 T ----------+ v v v [ NAND (T.U1.U0) ]--o--> CLR tens FF, CLR U3 U2 U1, PRESET U0 ``` #### Hours sequence | Pulse | T | U (BCD) | Display | |---|---|---|---| | start | 0 | 0001 | 01 | | 8 | 0 | 1001 | 09 | | 9 | 1 | 0000 | 10 | | 10 | 1 | 0001 | 11 | | 11 | 1 | 0010 | 12 | | 12 | 1 → 0 | 0011 → 0001 | 13 → 01 | #### Display Each BCD output feeds a BCD-to-7-segment decoder (7447) and display. The hours tens digit shows only "1" or blank, so segments b and c can be driven directly from T. An extra flip-flop toggled at 11 → 12 can drive an AM/PM indicator. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is special about the 12-hour clock's hours counter? A. It must go 12 -> 01 instead of 12 -> 00 or 13 B. It counts 0 to 11 C. It counts 1 to 24 D. It needs no tens digit Answer: A. Hours run 01 to 12 and then return to 01, not 00. (Key point: Hours sequence) 2. Which state is detected to recycle the hours counter and why? A. 12, the last valid count B. 13 (T = U1 = U0 = 1), the first state after 12 C. 10, where T first becomes 1 D. 24 Answer: B. After 12 the next pulse gives 13, and NAND(T, U1, U0) detects it. (Key point: Recycle detection) 3. What does the low LOAD output do? A. Clears tens and U3, U2, U1 and presets U0 so 13 becomes 01 B. Clears everything to 00 C. Sets all bits to 1 D. Stops the clock Answer: A. Clearing T, U3, U2, U1 and presetting U0 gives 0001, i.e. 01. (Key point: Load action) 4. How is the hours tens flip-flop clocked? A. By the 1 Hz signal B. By U3 when the units go 9 -> 0 C. By the minutes tens D. By the NAND output Answer: B. When units fall from 9 to 0 (09 -> 10), U3 falls and toggles the tens FF. (Key point: Tens digit clocking) ## Related in Digital Logic - [24-hour digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-24hr) — Digital Logic, chapter 8 - [Seconds section of a digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-seconds-section) — Digital Logic, chapter 8 - [Operation of a digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-operation) — Digital Logic, chapter 8 - [Digital clock with decoders for h, min, s](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-hour-minute-second) — Digital Logic, chapter 8 - [SIPO with 1010 data up to 9th clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1010-ninth-clock) — Digital Logic, chapter 7 - [Asynchronous mod-12 up counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-jk) — Digital Logic, chapter 8 ## Related in other subjects - [Digital clock state diagram](https://www.bctengineer.com/question.md?key=semester_6%2Fobject_oriented_analysis_and_design%3Adigital-clock-state-diagram) — Object Oriented Analysis and Design, chapter 2 - [Dual slope ADC numerical (12 kHz clock)](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adual-slope-numerical-12khz) — Advanced Electronics, chapter 3 - [30th hour volume and design controls](https://www.bctengineer.com/question.md?key=semester_6%2Ftransportation_engineering_i%3Adesign-volume-controls) — Transportation Engineering I, chapter 3 - [2-hr UH from figure: area, flood, Tc, two storms](https://www.bctengineer.com/question.md?key=semester_5%2Fengineering_hydrology%3Auh-2hr-figure-four-parts) — Engineering Hydrology, chapter 5