---
title: "24-hour digital clock"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:digital-clock-24hr"
source: https://www.bctengineer.com/q/semester_3/digital_logic/digital-clock-24hr
site: BCT Engineering
---

# 24-hour digital clock

Digital Logic · Chapter 8: Counters

- Asked in: 2078 Bhadra, 5 marks
- Video: [Building a 24 Hour Clock on Breadboards](https://www.youtube.com/watch?v=eNxahTZp07A) — Engineering Student Tries
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/digital-clock-24hr
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

Design and describe 24 hr digital clock.

## Short answer

A 24-hr clock uses a 1 Hz timebase derived from 50 Hz AC via shaping and division by 50. Seconds and minutes each use a mod-60 counter (mod-10 units, mod-6 tens cleared at 6). Hours use a mod-10 units and 2-bit tens counter cleared at 24 by NAND(T1, U2). BCD outputs drive 7447 decoders and 7-segment displays.

## Answer

A **24-hour digital clock** shows time from 00:00:00 to 23:59:59. It is a chain of counters fed by a 1 Hz time base, with BCD-to-7-segment decoders and displays.

#### Block diagram
```text
 AC 50 Hz -> [Shaper] -> [÷50] -> 1 Hz
                                  |
   +------------------------------+
   v
 [SECONDS ÷60: ÷10 -> ÷6] --> 1 pulse/min
   |  (2 decoders + 2 displays)
   v
 [MINUTES ÷60: ÷10 -> ÷6] --> 1 pulse/h
   |  (2 decoders + 2 displays)
   v
 [HOURS units ÷10] ---Q3---> [HOURS tens 0-2]
   | U3 U2 U1 U0               | T1 T0
   |       U2 ------+    +---- T1
   |                v    v
   |               [ NAND ]--o CLR (both)
 [7447]+[disp]       [7447]+[disp]
```

#### Design of each section
1. **1 Hz time base:** the 50 Hz mains is stepped down and squared by a Schmitt trigger, then divided by 50 (÷10 then ÷5) to give 1 pulse per second.
2. **Seconds (÷60):** mod-10 units counter (0–9) whose $Q_3$ clocks a mod-6 tens counter (0–5, cleared at 0110 by NAND of $Q_2$, $Q_1$). The tens reset gives 1 pulse per minute.
3. **Minutes (÷60):** identical to the seconds section; gives 1 pulse per hour.
4. **Hours (÷24):** a mod-10 units counter (U) and a 2-bit tens counter (T: 0, 1, 2). The units $Q_3$ falling at 9 → 0 clocks the tens counter.
   - The count must go 23 → 00. Count 24 = tens 10, units 0100.
   - Between 20 and 24, $T_1 = 1$ and $U_2 = 1$ occur together for the first time at 24. So a NAND gate of $T_1$ and $U_2$ drives the active-low CLEAR of both hour counters:
$$
\overline{CLR} = \overline{T_1\,U_2}
$$
   - Thus the hours count 00, 01, …, 09, 10, …, 19, 20, 21, 22, 23, 00.
5. **Display:** each BCD output drives a 7447 BCD-to-7-segment decoder and a common-anode display (six digits: HH:MM:SS).

| Section | Counters | Reset condition |
|---|---|---|
| Seconds | ÷10, ÷6 | tens = 6 (0110) |
| Minutes | ÷10, ÷6 | tens = 6 (0110) |
| Hours | ÷10, ÷3 | hours = 24 ($T_1U_2 = 1$) |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How is a 1 Hz signal obtained from 50 Hz mains?
   A. Shape it with a Schmitt trigger and divide by 50 (÷10 then ÷5)
   B. Multiply by 50
   C. Divide by 60
   D. Rectify and filter it
   Answer: A. The mains is squared by a Schmitt trigger, then divided by 10 and by 5 to get 1 pulse per second. (Key point: 1 Hz time base)

2. How is a ÷60 section built?
   A. A mod-6 units and mod-10 tens counter
   B. A mod-10 units counter followed by a mod-6 tens counter
   C. Two mod-10 counters
   D. A single mod-60 ripple stage with no reset
   Answer: B. Units count 0-9, then tens count 0-5, resetting at 6 (0110), giving 60 states. (Key point: Seconds/minutes sections)

3. Why is the hours counter cleared with NAND of T1 and U2?
   A. Count 24 (tens 10, units 0100) is the first state with T1 = U2 = 1, so it resets 23 -> 00
   B. Count 20 needs resetting
   C. It resets at 12
   D. It clears at 59
   Answer: A. Between 20 and 24, T1 and U2 are both 1 for the first time at 24, so that state triggers the clear. (Key point: 24-hour reset)

4. What drives the seven-segment displays?
   A. The 1 Hz oscillator
   B. A BCD-to-7-segment decoder like the 7447 for each digit
   C. The reset NAND gate
   D. A shift register
   Answer: B. Each BCD output goes to a 7447 decoder/driver that lights the right segments. (Key point: Display driving)

## Related in Digital Logic

- [12-hour digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-12hr) — Digital Logic, chapter 8
- [Seconds section of a digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-seconds-section) — Digital Logic, chapter 8
- [Operation of a digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-operation) — Digital Logic, chapter 8
- [Digital clock with decoders for h, min, s](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-hour-minute-second) — Digital Logic, chapter 8
- [SIPO with 1010 data up to 9th clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1010-ninth-clock) — Digital Logic, chapter 7

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- [Digital clock state diagram](https://www.bctengineer.com/question.md?key=semester_6%2Fobject_oriented_analysis_and_design%3Adigital-clock-state-diagram) — Object Oriented Analysis and Design, chapter 2
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