--- title: "Digital clock with decoders for h, min, s" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:digital-clock-hour-minute-second" source: https://www.bctengineer.com/q/semester_3/digital_logic/digital-clock-hour-minute-second site: BCT Engineering --- # Digital clock with decoders for h, min, s Digital Logic · Chapter 8: Counters - Asked in: 2074 Asoj, 6 marks - Video: [Application of Counter Digital Clock](https://www.youtube.com/watch?v=uCmOGc_Nfl0) — Dr Padmini S Panneer Selvam - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/digital-clock-hour-minute-second - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Draw the block diagram with decoders to show hour, minute and second. ## Short answer A digital clock uses a 1 Hz signal from a shaper and dividers. Seconds and minutes sections are mod-10 then mod-6 counters with BCD-to-7-segment decoders. The hours section uses a mod-10 units counter and a tens flip-flop with reset logic for a 12-hour display. ## Answer A digital clock is a chain of counters driven by a 1 Hz signal. Each counter's BCD output goes to a **BCD-to-7-segment decoder** (e.g. 7447/7448) which drives a seven-segment display, so hours, minutes and seconds are shown as decimal digits. #### Block diagram ```text AC 50 Hz -> [Shaper] -> [÷10] -> [÷5] -> 1 Hz | +--------------------------------------+ v SECONDS (00-59) [÷10 units] -----> [÷6 tens] -------+ 1 pulse/min | | | [7447 dec] [7447 dec] | [7-seg disp] [7-seg disp] | +---------------------------------+ v MINUTES (00-59) [÷10 units] -----> [÷6 tens] -------+ 1 pulse/h | | | [7447 dec] [7447 dec] | [7-seg disp] [7-seg disp] | +---------------------------------+ v HOURS (01-12) [÷10 units] -----> [tens FF] <--- reset/load logic | | [7447 dec] [decoder] [7-seg disp] [7-seg disp] ``` #### Working of each block 1. **Time base:** the 50 Hz mains (in Nepal) is stepped down and shaped into a square wave by a Schmitt trigger. Dividing by 10 and then by 5 gives exactly 1 pulse per second. (With 60 Hz mains the divider is ÷60; a 32.768 kHz crystal with a 15-stage ÷2 chain is also common.) 2. **Seconds section:** a mod-10 counter (7490) counts seconds units 0–9. Each time it goes from 9 to 0, its $Q_3$ output falls and clocks the mod-6 tens counter (0–5). When the tens counter reaches 6 (0110), it is reset to 0, and this reset produces one pulse per minute. 3. **Minutes section:** identical to the seconds section (mod-10 then mod-6, 00–59), clocked by the 1 pulse/min signal. Its output gives 1 pulse per hour. 4. **Hours section:** a mod-10 units counter and a single flip-flop for the tens digit (0 or 1). Gating logic makes the hours run 01 → 12 and then 01 (a 12-hour clock): when the count reaches 13, the units counter is loaded with 1 and the tens flip-flop is cleared. For a 24-hour clock, the tens counter is mod-3 and both counters are cleared at 24. 5. **Decoders and displays:** each BCD counter output (4 lines) feeds a BCD-to-7-segment decoder/driver, which turns on the correct segments a–g of a common-anode (7447) or common-cathode (7448) display. The hours tens digit needs only "1" or blank, so a simple driver is enough. #### Summary of counters | Section | Units counter | Tens counter | Output pulse | |---|---|---|---| | Seconds | mod-10 | mod-6 | 1 per minute | | Minutes | mod-10 | mod-6 | 1 per hour | | Hours | mod-10 | 1 FF (mod-12 logic) | 1 per 12 h | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is a 1 Hz signal obtained from 50 Hz mains in the digital clock? A. Shape the mains with a Schmitt trigger, then divide by 10 and by 5 B. Divide by 6 and by 10 C. Use the mains frequency directly D. Multiply by 50 Answer: A. The shaped 50 Hz square wave is divided by 10 and then by 5 (total 50) to give 1 pulse per second. (Key point: Time base) 2. How are the seconds (and minutes) sections built? A. Mod-6 units followed by mod-10 tens B. Mod-10 units followed by mod-6 tens, counting 00-59 C. Two mod-12 counters D. A single mod-60 ripple chain without decoders Answer: B. Units run 0-9 and tens run 0-5, giving 00 to 59; the tens reset produces the next-stage pulse. (Key point: Seconds and minutes counters) 3. What does the 7447 decoder do? A. Divides the clock B. Converts BCD counter outputs into segment signals a-g for a 7-segment display C. Stores the hour value D. Generates the 1 Hz pulse Answer: B. Each BCD output feeds a BCD-to-7-segment decoder/driver which lights the correct segments. (Key point: Role of decoder) 4. How does the 12-hour clock hours section behave at count 13? A. It continues to 14 B. The units counter is loaded with 1 and the tens flip-flop cleared, giving 01 C. Both digits are cleared to 00 D. The tens flip-flop is set Answer: B. Gating logic makes the hours run 01 to 12 and back to 01 by loading 1 into units and clearing tens when 13 is reached. (Key point: Hours section) ## Related in Digital Logic - [24-hour digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-24hr) — Digital Logic, chapter 8 - [12-hour digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-12hr) — Digital Logic, chapter 8 - [Seconds section of a digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-seconds-section) — Digital Logic, chapter 8 - [Operation of a digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-operation) — Digital Logic, chapter 8 - [Frequency counter operation with block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afrequency-counter) — Digital Logic, chapter 11, asked 14× - [n-bit full adder block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3An-bit-full-adder) — Digital Logic, chapter 5 ## Related in other subjects - [Digital clock state diagram](https://www.bctengineer.com/question.md?key=semester_6%2Fobject_oriented_analysis_and_design%3Adigital-clock-state-diagram) — Object Oriented Analysis and Design, chapter 2 - [Block diagram of digital communication system](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Ablock-diagram-digital-comm) — Data Communication, chapter 1, asked 8× - [Digital control system block diagram and advantages](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Adcs-block-diagram-advantages) — Digital Control System, chapter 1, asked 3× - [Reasons for modulation; digital communication block diagram](https://www.bctengineer.com/question.md?key=semester_6%2Fcommunication_systems%3Amodulation-reasons-digital-adv-duplex) — Communication Systems, chapter 1