---
title: "Seconds section of a digital clock"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:digital-clock-seconds-section"
source: https://www.bctengineer.com/q/semester_3/digital_logic/digital-clock-seconds-section
site: BCT Engineering
---

# Seconds section of a digital clock

Digital Logic · Chapter 8: Counters

- Asked in: 2072 Chaitra, 6 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/digital-clock-seconds-section
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

How does second section of a digital clock work? Explain its working principle using block diagram.

## Short answer

The seconds section is a mod-60 counter: a mod-10 units counter (e.g., 7490) followed by a mod-6 tens counter, clocked by 1 Hz pulses. Each counter's BCD output drives a 7447 decoder to 7-segment displays. When the tens counter resets at 6, it provides a carry pulse to the minutes section.

## Answer

The **seconds section** of a digital clock counts 1 Hz pulses from 00 to 59 and sends one pulse per minute to the minutes section. It is a **mod-60 counter** made of a mod-10 (units) counter followed by a mod-6 (tens) counter, with decoders and displays.

#### Block diagram
```text
 1 Hz pulses (from ÷50 divider of 50 Hz mains)
      |
      v
 +-----------+  Q3 (falls 9->0)  +-----------+
 | MOD-10    |------------------>| MOD-6     |--> 1 pulse
 | units     |                   | tens      |   per minute
 | (7490)    |                   | (reset at |   to minutes
 +-----------+                   |  0110)    |
   | | | |  BCD                  +-----------+
 +-----------+                     | | |
 | 7447      |                   +-----------+
 | decoder   |                   | 7447      |
 +-----------+                   +-----------+
   |a..g                           |a..g
 [7-seg units]                   [7-seg tens]
```

#### Working principle
1. **1 Hz input:** the 50 Hz mains is shaped into pulses and divided by 50 (÷10 then ÷5) to give 1 pulse per second.
2. **Units counter (mod-10):** a decade counter such as 7490 counts 0, 1, …, 9 on successive seconds. On the 10th pulse it returns to 0; at this moment its MSB $Q_3$ goes from 1 to 0.
3. **Tens counter (mod-6):** the falling edge of the units $Q_3$ clocks the tens counter, so it advances once every 10 seconds: 0, 1, …, 5. It is a 3-bit ripple counter reset at 6 (0110) by a NAND gate of $Q_2$ and $Q_1$ (or a 7492 wired as ÷6).
4. **Carry to minutes:** when the display shows 59 and the next pulse arrives, units go 9 → 0 and tens go 5 → 6 → 0. The falling of the tens counter's $Q_2$ at this reset gives one pulse per minute, which clocks the minutes units counter.
5. **Decoding and display:** each counter's BCD outputs drive a BCD-to-7-segment decoder/driver (7447 for common-anode displays). The decoder lights segments a–g to show the digit, so the seconds read 00, 01, …, 59, 00.

#### Count sequence
| Pulses | Tens (BCD) | Units (BCD) | Display |
|---|---|---|---|
| 0 | 000 | 0000 | 00 |
| 9 | 000 | 1001 | 09 |
| 10 | 001 | 0000 | 10 |
| 59 | 101 | 1001 | 59 |
| 60 | 000 | 0000 | 00 (+1 minute) |

The minutes section is built exactly the same way; only the hours section uses different (mod-12 or mod-24) logic.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does the seconds section consist of?
   A. A mod-10 units counter followed by a mod-6 tens counter, forming mod-60
   B. A single mod-12 counter
   C. A mod-6 units and mod-10 tens counter
   D. Two mod-10 counters
   Answer: A. Units count 0-9 and tens count 0-5, giving 60 seconds. (Key point: Structure of seconds section)

2. What clocks the tens counter?
   A. The 1 Hz pulse directly
   B. The falling edge of the units counter's Q3 (9 to 0)
   C. The decoder output
   D. The minutes counter
   Answer: B. When units go from 9 to 0, Q3 falls 1 to 0 and advances the tens counter once every 10 s. (Key point: Clocking the tens)

3. When does the tens counter reset, and what is produced?
   A. At 6 (0110); a NAND of Q2 and Q1 gives a reset and one pulse per minute
   B. At 5 (0101); one pulse per second
   C. At 9 (1001); one pulse per hour
   D. At 10; one pulse per 10 seconds
   Answer: A. At 6 (Q2 = Q1 = 1) the counter resets to 0, and the fall of Q2 gives one pulse per minute for the minutes section. (Key point: Tens reset)

4. What is the role of the 7447 in the seconds section?
   A. It counts the pulses
   B. It converts BCD to 7-segment signals a-g
   C. It resets the counter
   D. It divides 50 Hz by 50
   Answer: B. The decoder/driver lights the correct segments to show each BCD digit. (Key point: Decoder role)

## Related in Digital Logic

- [Digital clock with decoders for h, min, s](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-hour-minute-second) — Digital Logic, chapter 8
- [Operation of a digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-operation) — Digital Logic, chapter 8
- [24-hour digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-24hr) — Digital Logic, chapter 8
- [12-hour digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-12hr) — Digital Logic, chapter 8
- [Frequency counter operation with block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afrequency-counter) — Digital Logic, chapter 11, asked 14×
- [n-bit full adder block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3An-bit-full-adder) — Digital Logic, chapter 5

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