--- title: "Edge triggered JK flip-flop circuit" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:edge-jk-circuit" source: https://www.bctengineer.com/q/semester_3/digital_logic/edge-jk-circuit site: BCT Engineering --- # Edge triggered JK flip-flop circuit Digital Logic · Chapter 6: Flip Flops - Asked in: 2068 Baisakh, 5 marks - Video: [J K Flip flop | Edge triggered | STLD | Lec-119](https://www.youtube.com/watch?v=xcOwZz28QPI) — Education 4u - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/edge-jk-circuit - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Draw the circuit diagram of edge triggered JK flip flop and explain it. ## Short answer A narrow pulse from an edge detector enables J and K input gates at the rising clock edge. For J=K=1, the output toggles once because the pulse width is less than the feedback delay, preventing race-around. The latch holds state otherwise. ## Answer An **edge-triggered J-K flip-flop** changes state only at one edge of the clock (rising edge for positive edge triggering). It consists of an edge (pulse-transition) detector and a J-K NAND circuit. #### Circuit diagram ```text CLK --+---------------->+-----+ | | AND |---> CLK* +--->[ NOT ]----->+-----+ (delay dt) CLK* = CLK . CLK'(delayed): a spike of width about dt at every rising edge of CLK ``` ```text +------+ S* +------+ J -------| |----->| | CLK* ----| NAND | | NAND |-----> Q Q' ------| G1 | Q'->| G3 | +------+ +------+ +------+ R* +------+ K -------| |----->| | CLK* ----| NAND | | NAND |-----> Q' Q ------| G2 | Q-->| G4 | +------+ +------+ G3 and G4 are cross-coupled (NAND latch). Q' is fed back to G1, Q is fed back to G2. ``` #### Explanation - **Edge detector:** the inverter delays CLK by its propagation delay $\Delta t$. For this short time after a rising edge both AND inputs are 1, so CLK* is a narrow positive spike. This spike enables G1 and G2 only at the edge. - **Input gates:** G1 receives J, CLK*, Q'; G2 receives K, CLK*, Q. Their outputs drive the active-low inputs of the G3-G4 latch. | J | K | At rising edge | Q+ | |---|---|---|---| | 0 | 0 | G1 = G2 = 1, latch holds | Q (no change) | | 0 | 1 | G2 = 0 if Q = 1 | 0 (reset) | | 1 | 0 | G1 = 0 if Q = 0 | 1 (set) | | 1 | 1 | G1 fires if Q = 0, G2 if Q = 1 | Q' (toggle) | Characteristic equation: $Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n$. The CLK* pulse ends before the change of Q can travel back to G1/G2, so for J = K = 1 the output toggles only **once** per clock edge. This removes the race-around problem of the level-triggered J-K flip-flop. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How does the edge detector produce the narrow CLK* pulse? A. It ANDs CLK with its delayed complement, so both are 1 only briefly after a rising edge B. It ORs CLK with its delayed complement C. It divides CLK by two with a flip-flop D. It ANDs CLK with Q Answer: A. After a rising edge CLK is 1 while the delayed inverted CLK is still 1 for about the inverter delay, giving a narrow spike. (Key point: Edge detector) 2. Which feedback connections feed the input NAND gates of the edge-triggered J-K flip-flop? A. Q to G1 and Q' to G2 B. Q' to G1 (with J) and Q to G2 (with K) C. Q' to both gates D. No feedback is used Answer: B. G1 receives J, CLK* and Q'; G2 receives K, CLK* and Q. (Key point: Feedback connections) 3. Why does J = K = 1 toggle only once per clock edge here? A. Because the flip-flop has no feedback B. Because CLK* ends before the changed Q can reach G1/G2 C. Because the NAND latch is disabled D. Because the clock frequency is halved Answer: B. The narrow CLK* pulse is over before the new output travels back, so no second toggle occurs; this removes race-around. (Key point: Toggle once per edge) 4. What is the characteristic equation of the J-K flip-flop? A. Q+ = J Q + K Q' B. Q+ = J'Q' + K Q C. Q+ = J Q' + K' Q D. Q+ = J + K' Answer: C. Q(n+1) = J Q' + K' Q. (Key point: Characteristic equation) ## Related in Digital Logic - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× - [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6 - [Positive edge JK flip-flop and its drawbacks](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apositive-edge-jk-drawbacks) — Digital Logic, chapter 6 - [Edge triggered SR flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-sr-flipflop) — Digital Logic, chapter 6, asked 3× - [Negative edge JK flip-flop; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-negative-edge-t-to-jk) — Digital Logic, chapter 6 - [Positive edge SR flip-flop and its state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-positive-edge-state-diagram) — Digital Logic, chapter 6 ## Related in other subjects - [Edge triggered D flip-flop with preset, clear](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ad-flip-flop-edge-triggered) — Basic Electronics Engineering, chapter 6 - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9