--- title: "Edge triggered JK flip-flop with excitation table" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:edge-jk-excitation" source: https://www.bctengineer.com/q/semester_3/digital_logic/edge-jk-excitation site: BCT Engineering --- # Edge triggered JK flip-flop with excitation table Digital Logic · Chapter 6: Flip Flops - Asked in: 2076 Chaitra, 6 marks - Video: [JK Flip Flop: Circuit, Working, Truth Table, Characteristics Table & Excitation Table](https://www.youtube.com/watch?v=8trVtmPMSbY) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/edge-jk-excitation - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Explain the operation of edge triggered J-K Flip-Flop with necessary diagram and excitation table. ## Short answer An edge-triggered JK flip-flop updates only at the active clock edge. J and K determine next state: hold (00), reset (01), set (10), toggle (11). Its excitation table gives required J,K for transitions: 0→0: J=0, K=x; 0→1: J=1, K=x; 1→0: J=x, K=1; 1→1: J=x, K=0. ## Answer An **edge-triggered J-K flip-flop** changes its output only at the active edge (here the rising edge) of the clock. At that instant J and K decide whether Q is held, reset, set or toggled; at all other times the inputs have no effect. #### Circuit The flip-flop is a clocked J-K circuit (two input-steering NAND gates G1, G2 plus a NAND latch G3, G4) driven by a narrow pulse CLK* produced by an edge detector. ```text CLK --+---------------->+-----+ | | AND |---> CLK* +--->[ NOT ]----->+-----+ (delay dt) CLK* = CLK . CLK'(delayed): a spike of width about dt at every rising edge of CLK ``` ```text +------+ S* +------+ J -------| |----->| | CLK* ----| NAND | | NAND |-----> Q Q' ------| G1 | Q'->| G3 | +------+ +------+ +------+ R* +------+ K -------| |----->| | CLK* ----| NAND | | NAND |-----> Q' Q ------| G2 | Q-->| G4 | +------+ +------+ G3 and G4 are cross-coupled (NAND latch). Q' is fed back to G1, Q is fed back to G2. ``` #### Operation CLK* is high only for a very short time $\Delta t$ (a few ns) after each rising edge, so gates G1 and G2 are enabled only at that instant. Because the pulse is shorter than the propagation delay of the latch, the output changes at most once per edge (no race-around). 1. **J = 0, K = 0:** G1 and G2 outputs stay 1, the latch keeps its state: $Q_{n+1} = Q_n$. 2. **J = 0, K = 1:** if Q = 1, G2 (inputs K, CLK*, Q all 1) gives 0 and resets the latch: Q = 0. If Q is already 0, nothing changes. 3. **J = 1, K = 0:** if Q = 0, then Q' = 1 and G1 gives 0, which sets the latch: Q = 1. 4. **J = 1, K = 1:** the gate fed by the "active" output fires: if Q = 0, G1 sets it; if Q = 1, G2 resets it. The output **toggles**. #### Truth (characteristic) table | CLK | J | K | Q+ | Action | |---|---|---|---|---| | no edge | x | x | Q | No change | | edge | 0 | 0 | Q | No change (hold) | | edge | 0 | 1 | 0 | Reset | | edge | 1 | 0 | 1 | Set | | edge | 1 | 1 | Q' | Toggle | Characteristic equation: $$ Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n $$ #### Excitation table The excitation table gives the inputs needed for a required transition $Q_n \to Q_{n+1}$ (x = don't care). It is used when designing counters and sequential circuits. | Q | Q+ | J | K | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | x | | 1 | 0 | x | 1 | | 1 | 1 | x | 0 | - 0 to 0: J must be 0 (hold or reset both keep 0), so K = x. - 0 to 1: J must be 1 (set or toggle), K = x. - 1 to 0: K must be 1 (reset or toggle), J = x. - 1 to 1: K must be 0 (hold or set), J = x. #### Timing diagram (positive edge, Q starts at 0) ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| J ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾| K _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾| Q _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__ ``` ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What produces the narrow pulse CLK* in the edge-triggered JK flip-flop? A. A counter B. CLK ORed with J C. A monostable on K D. CLK ANDed with its delayed inverse Answer: D. The NOT gate delay makes CLK and delayed CLK-bar both 1 briefly after the rising edge. (Key point: Edge detector) 2. Why does the output toggle only once per edge when J = K = 1? A. CLK* is shorter than the latch propagation delay B. J and K are disabled C. The latch is slower than the clock period D. Q' is not fed back Answer: A. The new output arrives after CLK* ends, so the gates are no longer enabled. (Key point: No race-around) 3. With J = K = 1 and Q = 0 at the edge, which gate fires? A. Neither B. G1 sets the latch (Q = 1) C. G2 resets the latch D. Both Answer: B. G1 has inputs J, CLK*, Q'; with Q' = 1 it gives 0 and sets the latch; if Q = 1, G2 resets. (Key point: Toggle) 4. For a transition 1 to 0, what J and K are required? A. J = X, K = 0 B. J = 0, K = X C. J = X, K = 1 D. J = 1, K = X Answer: C. K must be 1 (reset or toggle), J is a don't care. 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