--- title: "Edge triggered SR flip-flop" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:edge-sr-flipflop" source: https://www.bctengineer.com/q/semester_3/digital_logic/edge-sr-flipflop site: BCT Engineering --- # Edge triggered SR flip-flop Digital Logic · Chapter 6: Flip Flops - Asked in: 2080 Bhadra, 6 marks; 2075 Asoj, 6 marks (asked 2 times) - Video: [Edge Triggered SR Flip Flop or Clocked SR Flip Flop](https://www.youtube.com/watch?v=JnkNkBsn_Oo) — Engg-Course-Made-Easy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/edge-sr-flipflop - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Explain the operation of edge triggered S-R Flip-Flop with timing diagram and truth table. ## Short answer An edge-triggered S-R flip-flop changes state only at the active clock edge (e.g., rising edge) via a narrow pulse from an edge detector. At that edge, S=0,R=0 holds, S=0,R=1 resets Q to 0, S=1,R=0 sets Q to 1, and S=1,R=1 is invalid. Q remains unchanged at all other times. ## Answer An **edge-triggered S-R flip-flop** changes state only at the active edge of the clock (rising edge for positive-edge, falling edge for negative-edge). At all other times, changes on S and R have no effect. It is made of a clocked SR latch with a **pulse-transition (edge) detector** on the clock input. #### Circuit ```text +-------------+ S -------->| NAND NAND |--+-- Q | steering | | CLK-[edge]>| gates latch | | detector | NAND NAND |--+-- Q' R -------->| | +-------------+ Edge detector (positive edge): CLK --+----------[AND]--> narrow pulse +-[NOT]----[ ] (delay of NOT gives a short spike) ``` The NOT gate's delay makes $CLK$ and $\overline{CLK}$ both 1 for a few nanoseconds just after the rising edge, so the AND gives a very narrow pulse. Only during this pulse are the steering gates enabled and the latch can change. #### Truth table (positive-edge-triggered) | CLK | S | R | $Q_{n+1}$ | Action | |---|---|---|---|---| | 0, 1 or falling | X | X | $Q_n$ | No change | | Rising edge | 0 | 0 | $Q_n$ | No change | | Rising edge | 0 | 1 | 0 | Reset | | Rising edge | 1 | 0 | 1 | Set | | Rising edge | 1 | 1 | ? | Invalid | #### Timing diagram ```text edge 1 2 3 4 5 CLK __|‾‾|__|‾‾|__|‾‾|__|‾‾|__|‾‾|__ S ‾‾‾‾‾|___________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾ R _____|‾‾‾‾‾‾‾‾‾‾‾|______________ Q __|‾‾‾‾‾|___________|‾‾‾‾‾‾‾‾‾‾‾ ``` - Edge 1: $S=1, R=0$: Q sets to 1. - Edge 2: $S=0, R=1$: Q resets to 0. - Edge 3: $S=0, R=1$: Q stays 0. - Edge 4: $S=1, R=0$: Q sets to 1. - Edge 5: $S=1, R=0$: Q stays 1. Q changes only just after a rising edge, even though S and R change at other times. This sampling at one instant makes edge-triggered flip-flops suitable for synchronous counters and registers. A negative-edge-triggered SR flip-flop works the same way, but on the falling edge (shown by a bubble with the triangle at CLK). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. When does an edge-triggered SR flip-flop change state? A. Only at the active clock edge B. Only when CLK is low C. Whenever S or R changes D. Throughout the whole time CLK is high Answer: A. It samples S and R only at the clock edge; other changes have no effect. (Key point: Edge triggering) 2. How does the edge detector produce a narrow pulse at the rising edge? A. It uses a long RC delay on S B. It ANDs CLK with a delayed inverted CLK C. It XORs S and R D. It ORs CLK with its inverse Answer: B. The NOT gate's delay keeps CLK-bar high briefly after CLK rises, so the AND output is a short spike. (Key point: Edge detector) 3. What happens at a rising edge with S = 0, R = 1? A. Set (Q = 1) B. No change C. Reset (Q = 0) D. Invalid Answer: C. S=0, R=1 resets the flip-flop; S=1,R=0 sets it, S=R=0 holds and S=R=1 is invalid. (Key point: Truth table) 4. In the timing diagram, why does Q change only just after rising edges even though S and R change at other times? A. Q follows R always B. The clock is inverted C. The latch is slow D. S and R are ignored except at the clock edge Answer: D. The steering gates are enabled only during the narrow edge pulse, so inputs are sampled at one instant. (Key point: Timing) ## Close variants set in other exams - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× ## Related in Digital Logic - [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6 - [Positive edge SR flip-flop and its state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-positive-edge-state-diagram) — Digital Logic, chapter 6 - [SR drawbacks; D flip-flop operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-d-flipflop) — Digital Logic, chapter 6 - [SR flip-flop diagram, excitation table, equation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-flipflop-diagram-equation) — Digital Logic, chapter 6 - [Edge triggered JK flip-flop circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-circuit) — Digital Logic, chapter 6 - [SR flip-flop with tables, equation, timing](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-flipflop-full-description) — Digital Logic, chapter 6, asked 2× ## Related in other subjects - [Edge triggered D flip-flop with preset, clear](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ad-flip-flop-edge-triggered) — Basic Electronics Engineering, chapter 6 - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6×