---
title: "2-bit fast adder; full subtractor from half subtractors"
subject: "Digital Logic"
chapter: 5
key: "semester_3/digital_logic:fast-adder-full-subtractor"
source: https://www.bctengineer.com/q/semester_3/digital_logic/fast-adder-full-subtractor
site: BCT Engineering
---

# 2-bit fast adder; full subtractor from half subtractors

Digital Logic · Chapter 5: Arithmetic Circuits

- Asked in: 2078 Kartik, 5+2 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/fast-adder-full-subtractor
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-5

## Question

Define and design 2-bit binary fast adder. Draw the circuit diagram of full subtractor using half subtractor.

## Short answer

A 2-bit fast adder uses carry look-ahead: Gi = AiBi, Pi = Ai⊕Bi; C1 = G0+P0C0, C2 = G1+P1G0+P1P0C0; sums S0 = P0⊕C0, S1 = P1⊕C1. A full subtractor is built with two half subtractors: first gives D1 = A⊕B, B1 = A'B; second gives D = D1⊕Bin, B2 = (A⊕B)'Bin; OR yields Bo = B1+B2.

## Answer

#### 2-bit binary fast adder

A **fast adder (carry look-ahead adder)** is a parallel adder in which all carries are produced directly from the input bits and the input carry, instead of waiting for the carry to ripple through each stage. This makes the addition time almost independent of the number of bits.

For each bit:
$$
G_i = A_iB_i \ (\text{carry generate}), \qquad P_i = A_i \oplus B_i \ (\text{carry propagate})
$$

Carries for 2 bits ($A_1A_0 + B_1B_0 + C_0$):

$$
\begin{aligned} C_1 &= G_0 + P_0C_0 \\ C_2 &= G_1 + P_1C_1 = G_1 + P_1G_0 + P_1P_0C_0 \end{aligned}
$$

Sums:
$$
S_0 = P_0 \oplus C_0, \qquad S_1 = P_1 \oplus C_1
$$

```text
A0,B0 -[XOR]-P0   -[AND]-G0
A1,B1 -[XOR]-P1   -[AND]-G1

C1 = G0 + P0.C0           (1 AND, 1 OR)
C2 = G1 + P1.G0 + P1.P0.C0 (2 AND, 1 OR)

S0 = P0 xor C0 ; S1 = P1 xor C1  (2 XOR)
C2 is the output carry.
```

Since $C_2$ comes from a two-level AND–OR circuit, it is ready after the same delay as $C_1$.

#### Full subtractor using half subtractors

$$
D = A \oplus B \oplus B_{in}, \qquad B_o = A'B + (A \oplus B)'B_{in}
$$

- HS1 ($A$, $B$): $D_1 = A \oplus B$, $B_1 = A'B$
- HS2 ($D_1$, $B_{in}$): $D = D_1 \oplus B_{in}$, $B_2 = D_1'B_{in}$
- $B_o = B_1 + B_2$ (one OR gate)

```text
A --->[ HS1 ]--D1-->[ HS2 ]----------> D
B --->[     ]  Bin->[     ]
         |B1           |B2
         +----->[OR]<--+
                  +------------------> Bo
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What makes a fast (carry look-ahead) adder fast?
   A. All carries are produced directly from inputs
   B. Carry ripples faster
   C. It has fewer bits
   D. It uses subtraction
   Answer: A. No waiting for the previous stage. (Key point: Fast adder)

2. What is C2 in a 2-bit CLA?
   A. G1 + P1
   B. G1 + P1G0 + P1P0C0
   C. G0 + P0
   D. P1P0
   Answer: B. Expansion of G1 + P1C1. (Key point: C2)

3. What is S1?
   A. G1 xor C1
   B. P1 C1
   C. P1 xor C1
   D. G1 + P1
   Answer: C. Sum = propagate XOR carry-in. (Key point: Sum)

4. Bo of the full subtractor from half subtractors is
   A. B1 xor B2
   B. B1 B2
   C. D1
   D. B1 + B2 (OR of the two borrows)
   Answer: D. One OR gate combines HS1 and HS2 borrows. (Key point: FS borrow)

## Related in Digital Logic

- [Full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-half-subtractors) — Digital Logic, chapter 5
- [n-bit full adder block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3An-bit-full-adder) — Digital Logic, chapter 5
- [Half adder/subtractor; 1's and 2's complement subtraction](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahalf-adder-subtractor-complement) — Digital Logic, chapter 5
- [2-bit fast adder and its advantage](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-2bit) — Digital Logic, chapter 5
- [3-bit multiplier with binary parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abinary-multiplier-3bit) — Digital Logic, chapter 5
- [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4

## Related in other subjects

- [VHDL PROCESS; full adder with half adders](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-process-full-adder) — Embedded System, chapter 9
- [Two-tape TM as binary adder](https://www.bctengineer.com/question.md?key=semester_3%2Ftheory_of_computation%3Atm-two-tape-binary-adder) — Theory of Computation, chapter 4
- [VHDL models; full adder structural](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-models-full-adder-structural) — Embedded System, chapter 9