--- title: "Flip-flop as state machine; SR to JK" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:flipflop-state-machine-sr-to-jk" source: https://www.bctengineer.com/q/semester_3/digital_logic/flipflop-state-machine-sr-to-jk site: BCT Engineering --- # Flip-flop as state machine; SR to JK Digital Logic · Chapter 6: Flip Flops - Asked in: 2080 Baisakh, 2+5 marks - Video: [Lec - 50: Convert SR to JK Flip Flop | Digital Electronics](https://www.youtube.com/watch?v=Q6jiXpclSGU) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/flipflop-state-machine-sr-to-jk - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question How can we use flip-flop as a state machine? Convert SR flip-flop to JK flip-flop. ## Short answer A flip-flop acts as a single-bit state machine with two states, where next state depends on inputs and present state. To convert SR to JK, add input logic: S = J·Q' and R = K·Q. Connect J AND Q' to S, and K AND Q to R of an SR flip-flop; the invalid S=R=1 is avoided. ## Answer #### Flip-flop as a state machine A **state machine** is a circuit whose output depends on its present state and inputs, and which moves from one state to the next at each clock. A flip-flop is the simplest state machine: - It stores one bit, so it has **two states**, Q = 0 and Q = 1. The stored value is the present state. - At each clock edge, the next state is decided by the inputs and the present state through its characteristic equation (e.g. $Q_{n+1} = J\overline{Q} + \overline{K}Q$). - Its behaviour can be drawn as a **state diagram** with two circles and arrows labelled with inputs, exactly like any finite state machine: ```text JK = 1x +-------------------------+ | v +-------+ +-------+ | Q = 0 | | Q = 1 | +-------+ +-------+ ^ | +-------------------------+ JK = x1 Self-loop on Q=0: JK = 0x (00 or 01) Self-loop on Q=1: JK = x0 (00 or 10) ``` - With n flip-flops plus next-state logic, a machine with up to $2^n$ states (counter, sequence detector) is built. #### Converting S-R flip-flop to J-K flip-flop S-R excitation table: | Q | Q+ | S | R | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | x | 0 | Conversion table (Q+ from the J-K table, then S, R from the S-R excitation table): | J | K | Q | Q+ | S | R | |---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | x | | 0 | 0 | 1 | 1 | x | 0 | | 0 | 1 | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 1 | x | 0 | | 1 | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 1 | 0 | 0 | 1 | K-maps: ```text K-map for S Q\JK 00 01 11 10 0 0 0 1 1 1 x 0 0 x K-map for R Q\JK 00 01 11 10 0 x x 0 0 1 0 1 1 0 ``` $$ S = J\,\overline{Q}, \qquad R = K\,Q $$ ```text +-----+ +---------+ J -------->| | | | Q' ------->| AND |----->| S Q |---> Q +-----+ | | +-----+ CLK->|> SR | K -------->| | | | Q ------->| AND |----->| R Q' |---> Q' +-----+ +---------+ (Q and Q' are fed back from the outputs) ``` For J = K = 1, S = Q' and R = Q, so the circuit toggles and the forbidden S = R = 1 never occurs. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why is a flip-flop the simplest state machine? A. It has two states (Q = 0 and Q = 1) and the next state follows from the inputs and present state B. It has no states C. It has only one input D. It does not need a clock Answer: A. It stores one bit, giving two states, and moves between them at each clock via its characteristic equation. (Key point: Flip-flop as state machine) 2. How many states can a machine built from n flip-flops have at most? A. n B. 2n C. n^2 D. 2^n Answer: D. n flip-flops give up to 2^n states. (Key point: Number of states) 3. What are S and R in the S-R to J-K conversion? A. S = J, R = K B. S = J Q', R = K Q C. S = J Q, R = K Q' D. S = J + Q, R = K + Q' Answer: B. The K-maps give S = J Q' and R = K Q. (Key point: S-R to J-K result) 4. For J = K = 1, what are S and R in the converted circuit? A. S = Q, R = Q' B. S = 1, R = 1 C. S = Q', R = Q so the circuit toggles D. S = 0, R = 0 Answer: C. S = Q' and R = Q, so exactly one is 1 and the output toggles without S = R = 1. (Key point: Toggle check) ## Related in Digital Logic - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× - [JK over SR advantages; D flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-over-sr-d-flipflop) — Digital Logic, chapter 6 - [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [JK to SR flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-to-sr-conversion) — Digital Logic, chapter 6 - [T to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3At-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [Negative edge JK flip-flop; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-negative-edge-t-to-jk) — Digital Logic, chapter 6 ## Related in other subjects - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6× - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9