--- title: "Full adder using a single 1:4 DEMUX" subject: "Digital Logic" chapter: 4 key: "semester_3/digital_logic:full-adder-1to4-demux" source: https://www.bctengineer.com/q/semester_3/digital_logic/full-adder-1to4-demux site: BCT Engineering --- # Full adder using a single 1:4 DEMUX Digital Logic · Chapter 4: Data Processing Circuits - Asked in: 2080 Bhadra, 5 marks; 2080 Baisakh, 5 marks (asked 2 times) - Video: [Implement Full Adder using 1:8 DEMUX | Number System and Code | Digital Circuit Design in EXTC](https://www.youtube.com/watch?v=0CEDT576-A0) — Ekeeda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/full-adder-1to4-demux - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4 ## Question Realize a full-adder circuit using a single 1:4 demultiplexer and necessary logic gates. ## Short answer A 1:4 DEMUX with data=1 and selects A,B acts as a 2-to-4 decoder giving minterms Y0–Y3. Sum S = (Y1 OR Y2) XOR Cin, carry Cout = Y3 OR ((Y1 OR Y2) AND Cin). Requires one OR, one XOR, one AND, and one OR gate. ## Answer A 1:4 demultiplexer with its data input tied to logic 1 behaves as a 2-to-4 decoder: with $A, B$ on the select lines, each output $Y_i$ is one minterm of $A$ and $B$. The third input $C_{in}$ is then combined with these outputs using a few gates. #### Truth table of the full adder | A | B | $C_{in}$ | S | $C_{out}$ | |---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 1 | 1 | #### Expressing S and $C_{out}$ in terms of the DEMUX outputs With $S_1 = A$, $S_0 = B$ and data input $D = 1$: $$ Y_0 = A'B',\quad Y_1 = A'B,\quad Y_2 = AB',\quad Y_3 = AB $$ From the table, grouping by $AB$: | AB | DEMUX output | S | $C_{out}$ | |---|---|---|---| | 00 | $Y_0$ | $C_{in}$ | 0 | | 01 | $Y_1$ | $C_{in}'$ | $C_{in}$ | | 10 | $Y_2$ | $C_{in}'$ | $C_{in}$ | | 11 | $Y_3$ | $C_{in}$ | 1 | $$ \begin{aligned} S &= (Y_0 + Y_3)C_{in} + (Y_1 + Y_2)C_{in}' \\ &= (Y_1 + Y_2) \oplus C_{in} \\ C_{out} &= Y_3 + (Y_1 + Y_2)\,C_{in} \end{aligned} $$ (Here $Y_1 + Y_2 = A \oplus B$.) #### Circuit ```text +----------+ 1 --->| D Y0 |-- (not used) | 1:4 Y1 |--+ A --->| S1 Y2 |--+--[OR]--- P (= A xor B) B --->| S0 Y3 |------------ Y3 +----------+ P, Cin ---[XOR]-------------------- S P, Cin ---[AND]--- P.Cin --+ Y3 -------------------------+--[OR]-- Cout ``` Gates needed: one 2-input OR ($P = Y_1 + Y_2$), one XOR ($S = P \oplus C_{in}$), one AND ($P \cdot C_{in}$) and one OR ($C_{out} = Y_3 + P C_{in}$). **Check:** for $A=1, B=1, C_{in}=1$: $Y_3 = 1$, $P = 0$, so $S = 0 \oplus 1 = 1$ and $C_{out} = 1$, i.e. $1+1+1 = 11_2$. Correct. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is the 1:4 DEMUX connected for the full adder? A. Data input 1, selects A and B B. Data input Cin, selects A and B C. Data input A, selects B and Cin D. Data input 0, selects Cin Answer: A. With D = 1 and selects A, B the outputs are the minterms of A and B, and Cin is added with gates. (Key point: DEMUX as decoder) 2. What is S? A. (Y1 + Y2) ⊕ Cin B. Y3 + Cin C. (Y0 + Y3)·Cin' D. Y1·Cin Answer: A. S = Cin for AB = 00, 11 and Cin' for 01, 10, which is (Y1 + Y2) ⊕ Cin. (Key point: Sum equation) 3. What is Cout? A. Y3 + (Y1 + Y2)Cin B. Y0 + Cin C. Y3 · Cin D. Y1 + Y2 + Cin Answer: A. Carry is 1 for AB = 11, equals Cin for 01 and 10, and is 0 for 00. (Key point: Carry equation) ## Close variants set in other exams - [Full subtractor using a 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-1to4-demux) — Digital Logic, chapter 4, asked 6× ## Related in Digital Logic - [Full adder using a single 4:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-single-4to1-mux) — Digital Logic, chapter 4 - [Full adder using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-2x4-decoder) — Digital Logic, chapter 4, asked 2× - [Full adder using decoder; (57−43) by 2's complement](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-decoder-subtract) — Digital Logic, chapter 4 - [Decoder; 2-to-4 decoder as a full adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adecoder-2to4-full-adder) — Digital Logic, chapter 4 - [Full adder using 4:1 multiplexers](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-4to1-mux) — Digital Logic, chapter 4 - [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5 ## Related in other subjects - [Short note: Logic gates](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-logic-gates) — Basic Electrical and Electronics Engineering, chapter 3 - [VHDL models; full adder structural](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-models-full-adder-structural) — Embedded System, chapter 9 - [VHDL PROCESS; full adder with half adders](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-process-full-adder) — Embedded System, chapter 9 - [Choppers; single-phase full bridge inverter](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Achoppers-full-bridge-inverter) — Advanced Electronics, chapter 7, asked 2×