---
title: "Full adder using a 2×4 decoder"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:full-adder-2x4-decoder"
source: https://www.bctengineer.com/q/semester_3/digital_logic/full-adder-2x4-decoder
site: BCT Engineering
---

# Full adder using a 2×4 decoder

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2080 Baisakh, 8 marks; 2078 Bhadra, 4 marks (asked 2 times)
- Video: [Implementation of full adder using two 2 to 4 decoders and nand gate](https://www.youtube.com/watch?v=9QWQtvtUeWY) — Digital2Real Tutorials
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/full-adder-2x4-decoder
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Realize Full Adder Circuit using a 2×4 decoder and using logic gates.

## Short answer

Use a 2×4 decoder with A,B as inputs to produce minterms Y0–Y3. Sum S = C_in XOR (Y1 + Y2) and carry C_o = Y3 + C_in·(Y1 + Y2). This requires one XOR, two OR, and one AND gate.

## Answer

A **full adder** adds three bits A, B and carry-in $C_{in}$ and gives sum S and carry-out $C_o$.

#### Truth table

| A | B | $C_{in}$ | S | $C_o$ |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |

$$
S = \Sigma m(1,2,4,7), \qquad C_o = \Sigma m(3,5,6,7)
$$

#### Realization with logic gates

From K-maps / algebra:
$$
\begin{aligned} S &= A \oplus B \oplus C_{in} \\ C_o &= AB + BC_{in} + AC_{in} = AB + C_{in}(A \oplus B) \end{aligned}
$$

```text
A, B ────────[XOR]── P = A⊕B
P, Cin ──────[XOR]──────────────── S

P, Cin ──────[AND]── Cin·P ──┐
                             ├─[OR]── Co
A, B ────────[AND]── AB ─────┘
```

(Two XOR, two AND and one OR gate.)

#### Realization with a 2×4 decoder

A 2×4 decoder has only two inputs, so it cannot generate all 8 minterms. Feed A and B to the decoder; its outputs are the minterms of A, B:
$$
Y_0 = \overline{A}\,\overline{B},\quad Y_1 = \overline{A}B,\quad Y_2 = A\overline{B},\quad Y_3 = AB
$$

Write S and $C_o$ for each AB combination in terms of $C_{in}$:

| AB | Decoder output | S | $C_o$ |
|---|---|---|---|
| 00 | $Y_0$ | $C_{in}$ | 0 |
| 01 | $Y_1$ | $\overline{C_{in}}$ | $C_{in}$ |
| 10 | $Y_2$ | $\overline{C_{in}}$ | $C_{in}$ |
| 11 | $Y_3$ | $C_{in}$ | 1 |

$$
\begin{aligned} S &= C_{in}(Y_0+Y_3) + \overline{C_{in}}(Y_1+Y_2) = C_{in} \oplus (Y_1+Y_2) \\ C_o &= Y_3 + C_{in}(Y_1+Y_2) \end{aligned}
$$

($Y_1 + Y_2 = A \oplus B$, so these are the same equations as the gate realization.)

```text
          +----------+
 A ──────>| I1    Y0 |── (not used)
 B ──────>| I0    Y1 |── Y1
          |  2x4  Y2 |── Y2
          |  DEC  Y3 |── Y3
          +----------+

Y1, Y2 ──────[OR]── P (= A⊕B)
P, Cin ──────[XOR]─────────────── S

P, Cin ──────[AND]── Cin·P ──┐
                             ├─[OR]── Co
Y3 ──────────────────────────┘
```

Gates needed besides the decoder: two OR gates, one XOR gate and one AND gate.

**Check:** A=1, B=1, $C_{in}$=0: $Y_3 = 1$, $P = 0$, so $S = 0 \oplus 0 = 0$ and $C_o = Y_3 = 1$; correct ($1+1 = 10_2$).

(With a 3×8 decoder, the usual method $S = Y_1+Y_2+Y_4+Y_7$, $C_o = Y_3+Y_5+Y_6+Y_7$ would need no XOR gate.)

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why can a 2×4 decoder not directly give all minterms of a full adder?
   A. It has only two inputs, so it cannot generate all 8 minterms of three variables
   B. It is slower than gates
   C. It has no enable
   D. It gives maxterms only
   Answer: A. Three inputs need a 3×8 decoder; here A, B feed the decoder and Cin is handled with gates. (Key point: Decoder limitation)

2. What is S in terms of decoder outputs and Cin?
   A. Cin ⊕ (Y1 + Y2)
   B. Cin + Y3
   C. Cin · (Y1 + Y2)
   D. Y0 ⊕ Y3
   Answer: A. S = Cin for AB = 00, 11 and Cin' for AB = 01, 10, so S = Cin ⊕ (Y1 + Y2). (Key point: Sum expression)

3. What is Co?
   A. Y1 + Cin·Y3
   B. Y3 + Cin(Y1 + Y2)
   C. Y0 + Cin
   D. Y3 · Cin
   Answer: B. For AB = 11 carry is 1, for 01 and 10 it equals Cin, and for 00 it is 0. (Key point: Carry expression)

4. When AB = 00 (Y0 active), what are S and Co?
   A. S = Cin', Co = Cin
   B. S = Cin, Co = 0
   C. S = 0, Co = Cin
   D. S = 1, Co = 0
   Answer: B. 0 + 0 + Cin gives sum Cin and no carry. (Key point: Sum for AB = 00)

## Related in Digital Logic

- [Full adder using decoder; (57−43) by 2's complement](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-decoder-subtract) — Digital Logic, chapter 4
- [Decoder; 2-to-4 decoder as a full adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adecoder-2to4-full-adder) — Digital Logic, chapter 4
- [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4
- [Full adder using a single 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-1to4-demux) — Digital Logic, chapter 4, asked 5×
- [Full subtractor using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-2x4-decoder) — Digital Logic, chapter 4, asked 4×
- [Full adder using a single 4:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-single-4to1-mux) — Digital Logic, chapter 4

## Related in other subjects

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- [VHDL models; full adder structural](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-models-full-adder-structural) — Embedded System, chapter 9
- [VHDL PROCESS; full adder with half adders](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-process-full-adder) — Embedded System, chapter 9
