---
title: "Full adder using 4:1 multiplexers"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:full-adder-4to1-mux"
source: https://www.bctengineer.com/q/semester_3/digital_logic/full-adder-4to1-mux
site: BCT Engineering
---

# Full adder using 4:1 multiplexers

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2073 Shrawan, 5 marks
- Video: [Full Adder Implementation using 4 to 1 Multiplexer: Designing and Circuit](https://www.youtube.com/watch?v=bgRvQas0ZHI) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/full-adder-4to1-mux
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Implement a full adder circuit using 4:1 Multiplexers.

## Short answer

Use two 4:1 MUXes with A and B as select lines. For Sum, data inputs are I0=Cin, I1=Cin', I2=Cin', I3=Cin. For Carry, data inputs are I0=0, I1=Cin, I2=Cin, I3=1. This directly realizes the full adder truth table.

## Answer

A full adder has inputs $A$, $B$, $C_{in}$ and outputs Sum $S$ and Carry $C_{out}$. Two 4:1 MUXes are used, one for each output, with $A$ and $B$ on the select lines ($S_1 = A$, $S_0 = B$) and $C_{in}$ on the data side.

#### Truth table

| A | B | $C_{in}$ | S | $C_{out}$ |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |

$$
S = \Sigma m(1,2,4,7), \qquad C_{out} = \Sigma m(3,5,6,7)
$$

#### Implementation tables

For data input $I_j$ ($AB = j$), the two rows are $C_{in} = 0$ (minterm $2j$) and $C_{in} = 1$ (minterm $2j+1$).

Sum:

| | $I_0$ | $I_1$ | $I_2$ | $I_3$ |
|---|---|---|---|---|
| $C_{in}'$ | 0 | **2** | **4** | 6 |
| $C_{in}$ | **1** | 3 | 5 | **7** |
| Input | $C_{in}$ | $C_{in}'$ | $C_{in}'$ | $C_{in}$ |

Carry:

| | $I_0$ | $I_1$ | $I_2$ | $I_3$ |
|---|---|---|---|---|
| $C_{in}'$ | 0 | 2 | 4 | **6** |
| $C_{in}$ | 1 | **3** | **5** | **7** |
| Input | 0 | $C_{in}$ | $C_{in}$ | 1 |

#### Circuit

```text
               +-------+                  +-------+
  Cin -------->| I0    |      0 --------->| I0    |
  Cin --[NOT]->| I1 4:1|-> S  Cin ------->| I1 4:1|-> Cout
  Cin'-------->| I2    |      Cin ------->| I2    |
  Cin -------->| I3    |      1 --------->| I3    |
               +-------+                  +-------+
                 A  B                       A  B
```

#### Check

From the MUX equation:

$$
C_{out} = A'B(C_{in}) + AB'(C_{in}) + AB(1) = (A \oplus B)C_{in} + AB
$$

which is the standard carry expression. For $A = 1, B = 0, C_{in} = 1$: select $10$ gives $S = I_2 = C_{in}' = 0$ and $C_{out} = I_2 = C_{in} = 1$, i.e. $1 + 0 + 1 = 10_2$. All eight rows were verified.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In the full adder using 4:1 MUXes, what goes on the select lines?
   A. Cin and A
   B. A and B
   C. B and Cin
   D. S and Cout
   Answer: B. A and B are S1 and S0; Cin appears on the data side. (Key point: Select line assignment)

2. How many 4:1 MUXes are used, and why?
   A. One for both outputs
   B. Two, one for Sum and one for Carry
   C. Three
   D. Four
   Answer: B. Each output needs its own MUX since their data inputs differ. (Key point: Number of MUXes)

3. What are the Sum MUX data inputs I0, I1, I2, I3?
   A. Cin, Cin', Cin', Cin
   B. 0, Cin, Cin, 1
   C. Cin', Cin, Cin, Cin'
   D. 0, 1, 1, 0
   Answer: A. S = A ⊕ B ⊕ Cin, so it is Cin when A = B and Cin' when A differs from B. (Key point: Sum data inputs)

4. What are the Carry MUX data inputs I0, I1, I2, I3?
   A. Cin, Cin', Cin', Cin
   B. 1, Cin, Cin, 0
   C. 0, Cin, Cin, 1
   D. 0, 0, 1, 1
   Answer: C. No carry when AB = 00, carry when AB = 11, and Cin passes through when exactly one of A, B is 1. (Key point: Carry data inputs)

## Related in Digital Logic

- [Full adder using a single 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-1to4-demux) — Digital Logic, chapter 4, asked 5×
- [Full adder using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-2x4-decoder) — Digital Logic, chapter 4, asked 2×
- [Full adder using decoder; (57−43) by 2's complement](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-decoder-subtract) — Digital Logic, chapter 4
- [Decoder; 2-to-4 decoder as a full adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adecoder-2to4-full-adder) — Digital Logic, chapter 4
- [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5
- [Full adder using a single 4:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-single-4to1-mux) — Digital Logic, chapter 4

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