---
title: "Full adder using decoder; (57−43) by 2's complement"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:full-adder-decoder-subtract"
source: https://www.bctengineer.com/q/semester_3/digital_logic/full-adder-decoder-subtract
site: BCT Engineering
---

# Full adder using decoder; (57−43) by 2's complement

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2078 Kartik, 3+3 marks
- Video: [2's complement subtraction|  very easy](https://www.youtube.com/watch?v=JKXs4qjVkWw) — RAUL S
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/full-adder-decoder-subtract
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Realize full adder circuit using decoder and gates. Subtract (43)₁₀ from (57)₁₀ using 2's complement method.

## Short answer

Full adder: Use a 3-to-8 decoder with inputs A,B,C. OR minterms: S = Y1+Y2+Y4+Y7, Cout = Y3+Y5+Y6+Y7. Subtraction: 57-43 in 7-bit: 57 = 0111001, 2's complement of 43 = 1010101; sum = 10001110, discard carry → 0001110₂ = 14₁₀.

## Answer

#### Full adder using a decoder and gates

A full adder adds $A$, $B$ and carry-in $C$:

| A | B | C | S | $C_o$ |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |

$$
S = \Sigma m(1,2,4,7), \qquad C_o = \Sigma m(3,5,6,7)
$$

A 3-to-8 decoder (inputs $A, B, C$) produces every minterm; OR the required lines:

$$
S = Y_1 + Y_2 + Y_4 + Y_7, \qquad C_o = Y_3 + Y_5 + Y_6 + Y_7
$$

```text
          +-------+
  A ----->| 2  Y0 |
  B ----->| 1  Y1 |---> to S
  C ----->| 0  Y2 |---> to S
          |    Y3 |---> to Co
          |3:8 Y4 |---> to S
          |    Y5 |---> to Co
          |    Y6 |---> to Co
          |    Y7 |---> to S and Co
          +-------+
  Y1,Y2,Y4,Y7 --[OR 4]--> S
  Y3,Y5,Y6,Y7 --[OR 4]--> Co
```

#### (57)₁₀ − (43)₁₀ by 2's complement

Use 7 bits (57 needs 6 bits; one extra bit for sign safety).

$$
57 = 0111001_2, \qquad 43 = 0101011_2
$$

1's complement of 43: $1010100$. Add 1: 2's complement $= 1010101$.

```text
      0111001     (+57)
    + 1010101     (2's complement of 43)
    ---------
    1 0001110
    ^ end carry discarded
```

An end carry appears, so the result is positive and equals the remaining bits: $0001110_2 = 8 + 4 + 2 = 14$.

**Answer:** $(57)_{10} - (43)_{10} = (0001110)_2 = (14)_{10}$

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which minterm lists give the Sum and Carry of a full adder?
   A. S = Σm(1,2,4,7), Co = Σm(3,5,6,7)
   B. S = Σm(3,5,6,7), Co = Σm(1,2,4,7)
   C. S = Σm(0,3,5,6), Co = Σm(1,2,4,7)
   D. S = Σm(1,2,4,7), Co = Σm(1,2,3,4)
   Answer: A. Sum is 1 when an odd number of inputs are 1 (1,2,4,7); carry is 1 when at least two are 1 (3,5,6,7). (Key point: Full adder minterms)

2. How is a full adder built from a 3-to-8 decoder?
   A. Connect the decoder outputs directly to S and Co
   B. OR the required minterm outputs for S and for Co using two 4-input OR gates
   C. Use AND gates on the decoder inputs
   D. Use the decoder outputs as XOR inputs only
   Answer: B. The decoder produces each minterm; OR gates collect Y1,Y2,Y4,Y7 for S and Y3,Y5,Y6,Y7 for Co. (Key point: Decoder plus OR gates)

3. What is the 7-bit 2's complement of 43 (0101011)?
   A. 1010100
   B. 1010101
   C. 1010111
   D. 0101100
   Answer: B. The 1's complement is 1010100; adding 1 gives 1010101. (Key point: 2's complement of 43)

4. After adding 57 and the 2's complement of 43, an end carry appears. What does this mean?
   A. The result is negative and must be complemented
   B. The result is positive; discard the carry and keep the remaining bits
   C. The addition overflowed and is invalid
   D. The carry must be added back to the result
   Answer: B. In 2's complement subtraction an end carry means the result is positive; it is discarded, leaving 0001110 = 14. (Key point: End carry meaning)

## Related in Digital Logic

- [Full adder using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-2x4-decoder) — Digital Logic, chapter 4, asked 2×
- [Decoder; 2-to-4 decoder as a full adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adecoder-2to4-full-adder) — Digital Logic, chapter 4
- [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4
- [Full adder using a single 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-1to4-demux) — Digital Logic, chapter 4, asked 5×
- [Full subtractor using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-2x4-decoder) — Digital Logic, chapter 4, asked 4×
- [Full adder using a single 4:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-single-4to1-mux) — Digital Logic, chapter 4

## Related in other subjects

- [VHDL models; full adder structural](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-models-full-adder-structural) — Embedded System, chapter 9
- [VHDL PROCESS; full adder with half adders](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-process-full-adder) — Embedded System, chapter 9
- [2's complement subtraction; AND using NOR](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Atwo-complement-111-110-nor-and) — Basic Electronics Engineering, chapter 6
