---
title: "Full adder using a single 4:1 MUX"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:full-adder-single-4to1-mux"
source: https://www.bctengineer.com/q/semester_3/digital_logic/full-adder-single-4to1-mux
site: BCT Engineering
---

# Full adder using a single 4:1 MUX

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2079 Bhadra, 4 marks
- Video: [Full Adder Implementation using 4 to 1 Multiplexer: Designing and Circuit](https://www.youtube.com/watch?v=bgRvQas0ZHI) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/full-adder-single-4to1-mux
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Realize full-adder using a single 4:1 MUX and logical gates.

## Short answer

Connect A and B as select lines of a 4:1 MUX. For sum, set I0=I3=Cin, I1=I2=Cin' (with one NOT). Carry output is generated separately using gates: Cout = AB + Cin(A⊕B).

## Answer

A full adder adds $A$, $B$ and $C_{in}$ and gives
$$
S = A \oplus B \oplus C_{in}, \qquad C_{out} = AB + C_{in}(A \oplus B)
$$

Use $A$ and $B$ as the select lines ($S_1 = A$, $S_0 = B$) of the 4:1 MUX and express each output in terms of $C_{in}$.

#### Truth table grouped by A, B

| A | B | $C_{in}$ | S | $C_{out}$ |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |

| AB | S in terms of $C_{in}$ | $C_{out}$ in terms of $C_{in}$ |
|---|---|---|
| 00 ($I_0$) | $C_{in}$ | 0 |
| 01 ($I_1$) | $C_{in}'$ | $C_{in}$ |
| 10 ($I_2$) | $C_{in}'$ | $C_{in}$ |
| 11 ($I_3$) | $C_{in}$ | 1 |

#### Realization

- **Sum from the single 4:1 MUX:** $I_0 = C_{in}$, $I_1 = C_{in}'$, $I_2 = C_{in}'$, $I_3 = C_{in}$ (one NOT gate gives $C_{in}'$).
- **Carry from gates:** $C_{out} = AB + C_{in}(A\oplus B)$, using one XOR, two AND and one OR gate (or the simpler $C_{out} = AB + BC_{in} + AC_{in}$).

```text
Cin ------+----------> I0 +-------+
          +-[NOT]--+-> I1 | 4:1   |
                   +-> I2 | MUX   |--> S
Cin -----------------> I3 |       |
                          +-------+
                          S1=A S0=B

A --+--[AND]---------------+
B --+--[   ]               +--[OR]--> Cout
A,B --[XOR]--[AND]---------+
Cin ---------[   ]
```

Check: $A=1, B=0, C_{in}=1$ selects $I_2 = C_{in}' = 0$ so $S = 0$, and $C_{out} = 0 + 1\cdot1 = 1$. This matches $1+0+1 = 10_2$.

(If a second 4:1 MUX were allowed, $C_{out}$ would use $I_0=0, I_1=C_{in}, I_2=C_{in}, I_3=1$.)

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which signals are on the select lines of the 4:1 MUX?
   A. Cin and A
   B. Cin and B
   C. S and Cout
   D. A and B
   Answer: D. Data inputs are then functions of Cin. (Key point: Select lines)

2. What are the MUX inputs I0, I1, I2, I3 for the sum?
   A. Cin, Cin', Cin', Cin
   B. 0, Cin, Cin, 1
   C. Cin', Cin, Cin, Cin'
   D. 0, 1, 1, 0
   Answer: A. S = A xor B xor Cin; AB = 00 or 11 gives Cin, and AB = 01 or 10 gives Cin'. (Key point: Sum inputs)

3. How is Cout produced?
   A. From the same single MUX at the same time
   B. By separate gates, Cout = AB + Cin(A xor B)
   C. From a NOT gate only
   D. It equals S
   Answer: B. One MUX gives only one output; carry needs gates or a second MUX. (Key point: Carry)

4. For A=1, B=0, Cin=1, what are S and Cout?
   A. S = 1, Cout = 0
   B. S = 1, Cout = 1
   C. S = 0, Cout = 1
   D. S = 0, Cout = 0
   Answer: C. 1+0+1 = 10 in binary. (Key point: Check)

## Related in Digital Logic

- [Full adder using a single 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-1to4-demux) — Digital Logic, chapter 4, asked 5×
- [Full adder using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-2x4-decoder) — Digital Logic, chapter 4, asked 2×
- [Full adder using decoder; (57−43) by 2's complement](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-decoder-subtract) — Digital Logic, chapter 4
- [Decoder; 2-to-4 decoder as a full adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adecoder-2to4-full-adder) — Digital Logic, chapter 4
- [Σ(0,2,3,5,8,12,14) using 8:1 MUX; add with full adders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-add-full-adders) — Digital Logic, chapter 4
- [Full adder using 4:1 multiplexers](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-4to1-mux) — Digital Logic, chapter 4

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