--- title: "Full subtractor using a 1:4 DEMUX" subject: "Digital Logic" chapter: 4 key: "semester_3/digital_logic:full-subtractor-1to4-demux" source: https://www.bctengineer.com/q/semester_3/digital_logic/full-subtractor-1to4-demux site: BCT Engineering --- # Full subtractor using a 1:4 DEMUX Digital Logic · Chapter 4: Data Processing Circuits - Asked in: 2079 Bhadra, 5 marks; 2076 Chaitra, 5 marks; 2072 Chaitra, 6 marks (asked 3 times) - Video: [Full Subtractor using 1:8 Demultiplexer](https://www.youtube.com/watch?v=-9s3xBlcBVM) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/full-subtractor-1to4-demux - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4 ## Question Realize a full-subtractor logic circuit using a single 1:4 demultiplexer and necessary logic gates. ## Short answer Set the DEMUX data input to 1, use A,B as select lines to obtain minterms Y0–Y3. Difference D = B_in XOR (Y1 + Y2) and borrow B_o = Y1 + B_in·(Y0 + Y3). Implement with OR, XOR, AND gates. ## Answer A **full subtractor** subtracts $B$ and a borrow-in $B_{in}$ from $A$, giving difference $D$ and borrow-out $B_o$. #### Truth table | A | B | $B_{in}$ | D | $B_o$ | |---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 1 | $$ D = \Sigma m(1,2,4,7) = A \oplus B \oplus B_{in}, \qquad B_o = \Sigma m(1,2,3,7) $$ #### Using a 1:4 DEMUX as a 2-to-4 decoder Connect the data input of the 1:4 demultiplexer to logic 1 and use A, B as its select lines $S_1S_0$. Each output is then one minterm of A and B: $$ Y_0 = \overline{A}\,\overline{B},\quad Y_1 = \overline{A}B,\quad Y_2 = A\overline{B},\quad Y_3 = AB $$ Group the truth table by A, B and see how D and $B_o$ depend on $B_{in}$: | AB | Active output | D | $B_o$ | |---|---|---|---| | 00 | $Y_0$ | $B_{in}$ | $B_{in}$ | | 01 | $Y_1$ | $\overline{B_{in}}$ | 1 | | 10 | $Y_2$ | $\overline{B_{in}}$ | 0 | | 11 | $Y_3$ | $B_{in}$ | $B_{in}$ | So: $$ \begin{aligned} D &= B_{in}(Y_0+Y_3) + \overline{B_{in}}(Y_1+Y_2) = B_{in} \oplus (Y_1+Y_2) \\ B_o &= Y_1 + B_{in}(Y_0+Y_3) \end{aligned} $$ (Since exactly one Y is 1, $Y_0+Y_3 = \overline{Y_1+Y_2}$.) #### Circuit ```text +------------+ 1 ────>| Din Y0 |── Y0 | Y1 |── Y1 | 1:4 Y2 |── Y2 | DEMUX Y3 |── Y3 +------------+ S1 S0 A B Y1, Y2 ─────[OR]── Q Q, Bin ─────[XOR]─────────────── D Y0, Y3 ─────[OR]── P P, Bin ─────[AND]── Bin·P ──┐ ├─[OR]── Bo Y1 ─────────────────────────┘ ``` Gates needed: one 1:4 DEMUX, three 2-input OR gates, one AND gate and one XOR gate. **Check:** A=0, B=1, $B_{in}$=1 (minterm 3): $Y_1 = 1$, so $Q = 1$, $D = 1 \oplus 1 = 0$ and $B_o = Y_1 = 1$. This matches the truth table. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is the 1:4 DEMUX used to generate minterms of A and B? A. Data input tied to 0, A and B as data B. Data input tied to 1, A and B as select lines C. Data input is Bin D. Select lines are D and Bo Answer: B. With data = 1, each output Yi is the minterm of the select variables A, B. (Key point: DEMUX as decoder) 2. What is D in terms of the DEMUX outputs and Bin? A. Bin ⊕ (Y1 + Y2) B. Bin · (Y1 + Y2) C. Bin + Y3 D. Y0 ⊕ Y3 Answer: A. D = Bin for AB = 00 or 11 and Bin' for AB = 01 or 10, i.e. D = Bin ⊕ (Y1 + Y2). (Key point: Difference expression) 3. What is the borrow-out? A. Bo = Y2 + Bin(Y0 + Y3) B. Bo = Y1 + Bin(Y0 + Y3) C. Bo = Y3 + Bin(Y1 + Y2) D. Bo = Y1 + Y2 Answer: B. For AB = 01 borrow is 1; for 00 and 11 it equals Bin; for 10 it is 0. (Key point: Borrow expression) 4. Which extra gates are needed besides the DEMUX? A. Three OR, one AND, one XOR B. Two AND, two XOR C. Four NOT only D. Three AND, one OR Answer: A. ORs for Y1+Y2, Y0+Y3 and the final Bo, an AND for Bin·P, and an XOR for D. (Key point: Gate count) ## Close variants set in other exams - [Full adder using a single 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-1to4-demux) — Digital Logic, chapter 4, asked 5× - [Full subtractor using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-2x4-decoder) — Digital Logic, chapter 4, asked 4× ## Related in Digital Logic - [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4 - [Full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-half-subtractors) — Digital Logic, chapter 5 - [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5 - [PLA and full subtractor using PLA](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apla-full-subtractor) — Digital Logic, chapter 4 - [Full adder using a single 4:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-single-4to1-mux) — Digital Logic, chapter 4 - [Function Σm(0,2,3,5,7,8,10,13,15) using 1:8 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademux-1to8-realize-function) — Digital Logic, chapter 4 ## Related in other subjects - [Short note: Logic gates](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-logic-gates) — Basic Electrical and Electronics Engineering, chapter 3 - [Choppers; single-phase full bridge inverter](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Achoppers-full-bridge-inverter) — Advanced Electronics, chapter 7, asked 2× - [Single-phase full converter, 10 A, α = 30°](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_electronics%3Afull-converter-10a-30deg) — Power Electronics, chapter 2, asked 4× - [Full duplex on a single twisted pair](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Atwisted-pair-full-duplex-converter) — Telecommunications, chapter 2