--- title: "Full subtractor using decoder; combinational circuit" subject: "Digital Logic" chapter: 4 key: "semester_3/digital_logic:full-subtractor-decoder-combinational" source: https://www.bctengineer.com/q/semester_3/digital_logic/full-subtractor-decoder-combinational site: BCT Engineering --- # Full subtractor using decoder; combinational circuit Digital Logic · Chapter 4: Data Processing Circuits - Asked in: 2080 Bhadra, 4+2 marks - Video: [U2 L6.4 | Full Subtractor Using Decoder | implementation of Full Subtractor using 3: 8 Decoder](https://www.youtube.com/watch?v=dEk6M-ocfQA) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/full-subtractor-decoder-combinational - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4 ## Question Design the full-subtractor circuit using decoder and required logic gates. What is a combinational logic circuit? ## Short answer With a 3-to-8 decoder, difference D = Y1+Y2+Y4+Y7, borrow Bout = Y1+Y2+Y3+Y7, both via 4-input OR gates. A combinational circuit has outputs depending only on present inputs, with no memory or feedback. ## Answer #### Full subtractor using a decoder A full subtractor computes $A - B - B_{in}$ and gives the difference $D$ and borrow out $B_{out}$. | A | B | $B_{in}$ | D | $B_{out}$ | Minterm | |---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 1 | 1 | | 0 | 1 | 0 | 1 | 1 | 2 | | 0 | 1 | 1 | 0 | 1 | 3 | | 1 | 0 | 0 | 1 | 0 | 4 | | 1 | 0 | 1 | 0 | 0 | 5 | | 1 | 1 | 0 | 0 | 0 | 6 | | 1 | 1 | 1 | 1 | 1 | 7 | $$ D = \Sigma m(1,2,4,7), \qquad B_{out} = \Sigma m(1,2,3,7) $$ A 3-to-8 decoder with inputs $A, B, B_{in}$ (A = MSB) gives all 8 minterms at $Y_0$–$Y_7$. Each output function is the OR of its minterm lines: $$ D = Y_1 + Y_2 + Y_4 + Y_7, \qquad B_{out} = Y_1 + Y_2 + Y_3 + Y_7 $$ ```text +--------+ A ----->| 2 Y0 | B ----->| 1 Y1 |---> D, Bout Bin --->| 0 Y2 |---> D, Bout | 3:8 Y3 |---> Bout | Y4 |---> D | Y5 | | Y6 | | Y7 |---> D, Bout +--------+ Y1, Y2, Y4, Y7 ---[OR 4]---> D Y1, Y2, Y3, Y7 ---[OR 4]---> Bout ``` Two 4-input OR gates complete the design (with an active-low decoder like 74138, use 4-input NAND gates instead). #### Combinational logic circuit A **combinational logic circuit** is a circuit whose outputs at any instant depend only on the present values of its inputs. It has no memory and no feedback from output to input. It is built only from logic gates. Examples: adders, subtractors, multiplexers, decoders, encoders and comparators. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which OR combination gives D? A. Y1 + Y2 + Y4 + Y7 B. Y1 + Y2 + Y3 + Y7 C. Y3 + Y5 + Y6 + Y7 D. Y0 + Y3 + Y5 + Y6 Answer: A. D = Σm(1,2,4,7). (Key point: Difference with decoder) 2. Which OR combination gives Bout? A. Y1 + Y2 + Y4 + Y7 B. Y3 + Y5 + Y6 + Y7 C. Y1 + Y2 + Y3 + Y7 D. Y4 + Y5 + Y6 Answer: C. Bout = Σm(1,2,3,7); a 3:8 decoder with inputs A, B, Bin supplies the minterms. (Key point: Borrow with decoder) 3. What defines a combinational logic circuit? A. Outputs depend only on present inputs, with no memory or feedback B. Outputs depend on past states C. It contains flip-flops D. It needs a clock Answer: A. Adders, multiplexers, decoders and comparators are examples built only from gates. (Key point: Combinational circuit) 4. With an active-low decoder like 74138, which gates replace the OR gates? A. 4-input NAND gates B. NOR gates C. XOR gates D. AND gates Answer: A. Active-low outputs combined with NAND give the OR of the minterms. (Key point: Active-low decoder) ## Related in Digital Logic - [Full subtractor using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-2x4-decoder) — Digital Logic, chapter 4, asked 4× - [Define combinational logic circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acombinational-circuit-define) — Digital Logic, chapter 3 - [Combinational vs sequential; BCD-to-decimal decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-to-decimal-decoder) — Digital Logic, chapter 4 - [Full subtractor using a 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-1to4-demux) — Digital Logic, chapter 4, asked 6× - [Full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-half-subtractors) — Digital Logic, chapter 5 - [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5 ## Related in other subjects - [Short note: Logic gates](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-logic-gates) — Basic Electrical and Electronics Engineering, chapter 3 - [Use of VHDL; decoder design](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-use-decoder) — Embedded System, chapter 9 - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6