--- title: "3-bit Gray code synchronous counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:gray-code-sync-counter-3bit" source: https://www.bctengineer.com/q/semester_3/digital_logic/gray-code-sync-counter-3bit site: BCT Engineering --- # 3-bit Gray code synchronous counter Digital Logic · Chapter 8: Counters - Asked in: 2076 Chaitra, 8 marks; 2072 Chaitra, 7 marks (asked 2 times) - Video: [Designing a 3-Bit Gray Code Counter using T Flip-Flops | Synchronous Sequential Circuit Explained](https://www.youtube.com/watch?v=L6OJAdkjT2k) — Fakhar STEM Sphere - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/gray-code-sync-counter-3bit - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Design and draw the circuit diagram of a 3 bit gray code synchronous counter. ## Short answer A 3-bit Gray code synchronous counter uses 3 JK flip-flops with a common clock. The sequence is 000→001→011→010→110→111→101→100→000. Input equations: J2=Q1Q0', K2=Q1'Q0'; J1=Q2'Q0, K1=Q2Q0; J0=XNOR(Q2,Q1), K0=XOR(Q2,Q1). ## Answer A **3-bit Gray code counter** steps through the 3-bit Gray sequence, in which only one bit changes between successive counts: 000 → 001 → 011 → 010 → 110 → 111 → 101 → 100 → 000. A synchronous design with JK flip-flops is given below. #### Step 1: Flip-flops 8 states, so 3 JK flip-flops ($Q_2Q_1Q_0$) with a common clock. No unused states. JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0. #### Step 2: Excitation table | Present Q2Q1Q0 | Next Q2Q1Q0 | J2 | K2 | J1 | K1 | J0 | K0 | |---|---|---|---|---|---|---|---| | 000 | 001 | 0 | X | 0 | X | 1 | X | | 001 | 011 | 0 | X | 1 | X | X | 0 | | 011 | 010 | 0 | X | X | 0 | X | 1 | | 010 | 110 | 1 | X | X | 0 | 0 | X | | 110 | 111 | X | 0 | X | 0 | 1 | X | | 111 | 101 | X | 0 | X | 1 | X | 0 | | 101 | 100 | X | 0 | 0 | X | X | 1 | | 100 | 000 | X | 1 | 0 | X | 0 | X | #### Step 3: K-maps | J0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | 1 | X | X | 0 | | 1 | 0 | X | X | 1 | | K0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | X | 0 | 1 | X | | 1 | X | 1 | 0 | X | | J1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | 0 | 1 | X | X | | 1 | 0 | 0 | X | X | | K1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | X | X | 0 | 0 | | 1 | X | X | 1 | 0 | | J2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | 0 | 0 | 0 | 1 | | 1 | X | X | X | X | | K2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | X | X | X | X | | 1 | 1 | 0 | 0 | 0 | #### Step 4: Equations $$ \begin{aligned} &J_2 = Q_1\overline{Q_0},\quad K_2 = \overline{Q_1}\overline{Q_0} \\ &J_1 = \overline{Q_2}Q_0,\quad K_1 = Q_2Q_0 \\ &J_0 = Q_2Q_1 + \overline{Q_2}\overline{Q_1},\quad K_0 = Q_2\overline{Q_1} + \overline{Q_2}Q_1 \end{aligned} $$ So $J_0 = \overline{Q_2 \oplus Q_1}$ (XNOR) and $K_0 = Q_2 \oplus Q_1$ (XOR). #### Step 5: Circuit diagram ```text +-----+ +-----+ +-----+ J0>|J Q|-Q0 J1>|J Q|-Q1 J2>|J Q|-Q2 | FF0 | | FF1 | | FF2 | K0>|K | K1>|K | K2>|K | +--o--+ +--o--+ +--o--+ | | | CLK---+-------------+-------------+ J0 = XNOR(Q2,Q1) K0 = XOR(Q2,Q1) J1 = Q2'.Q0 K1 = Q2.Q0 J2 = Q1.Q0' K2 = Q1'.Q0' ``` Gates needed: one XOR, one XNOR (or XOR + NOT) and four 2-input AND gates. #### Step 6: Timing diagram ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___ Q1 ________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________ Q0 ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______ Cnt 000 001 011 010 110 111 101 100 000 ``` Only one output changes at each clock edge, which is the main advantage of a Gray code counter (no decoding glitches, low noise). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which sequence does the 3-bit Gray code counter follow? A. 000, 001, 010, 011, 100, 101, 110, 111 B. 000, 001, 011, 010, 110, 111, 101, 100 C. 000, 100, 110, 111, 011, 001, 000 D. 000, 001, 011, 111, 101, 100, 000 Answer: B. In Gray code only one bit changes between successive counts: 000, 001, 011, 010, 110, 111, 101, 100. (Key point: Gray sequence) 2. How many flip-flops are needed, and are there unused states? A. 3; no unused states since all 8 states are used B. 3; five unused states C. 8; no unused states D. 4; eight unused states Answer: A. Eight states need 3 flip-flops and all 8 combinations are used, so no don't cares from unused states. (Key point: Number of flip-flops and don't cares) 3. Which equations are correct? A. J2 = Q1 Q0', K2 = Q1' Q0'; J1 = Q2' Q0, K1 = Q2 Q0 B. J2 = Q1 Q0, K2 = Q1' Q0'; J1 = Q2 Q0, K1 = Q2' Q0 C. J2 = Q0, K2 = Q1; J1 = Q2', K1 = Q2 D. J2 = K2 = Q1 xor Q0; J1 = K1 = Q2 Answer: A. These come from the K-maps: J2 = Q1Q0', K2 = Q1'Q0', J1 = Q2'Q0, K1 = Q2Q0. (Key point: Equations for J2, K2, J1, K1) 4. Which gates give J0 and K0? A. J0 = XOR(Q2,Q1), K0 = XNOR(Q2,Q1) B. J0 = XNOR(Q2,Q1), K0 = XOR(Q2,Q1) C. J0 = K0 = 1 D. J0 = Q2 Q1, K0 = Q2' Q1' Answer: B. J0 = Q2Q1 + Q2'Q1' is the XNOR and K0 = Q2Q1' + Q2'Q1 is the XOR of Q2 and Q1. (Key point: J0 and K0 gates) ## Related in Digital Logic - [Sync vs async; 3-bit Gray code counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Agray-sync-counter-advantages) — Digital Logic, chapter 8 - [Mod-5 Gray code synchronous up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-gray-sync-counter) — Digital Logic, chapter 8 - [Gray code and 3-bit binary-to-Gray converter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Agray-code-binary-gray-converter) — Digital Logic, chapter 1 - [BCD code and 3-bit binary-to-Gray converter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-code-gray-converter) — Digital Logic, chapter 1 - [Sync vs async; 3-bit synchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-down-counter-3bit) — Digital Logic, chapter 8 - [Sync vs async; 3-bit synchronous up counter (T)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-up-counter-3bit-t) — Digital Logic, chapter 8 ## Related in other subjects - [Structural modelling; 3-bit up counter](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-structural-3bit-counter) — Embedded System, chapter 9