---
title: "Sync vs async; 3-bit Gray code counter"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:gray-sync-counter-advantages"
source: https://www.bctengineer.com/q/semester_3/digital_logic/gray-sync-counter-advantages
site: BCT Engineering
---

# Sync vs async; 3-bit Gray code counter

Digital Logic · Chapter 8: Counters

- Asked in: 2074 Asoj, 2+6 marks
- Video: [3-Bit Synchronous Up Counter](https://www.youtube.com/watch?v=6e8oV2blkGs) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/gray-sync-counter-advantages
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

List the advantages and disadvantages of a synchronous counter over asynchronous counter. Design a 3 bit synchronous counter which follow gray code sequence.

## Short answer

Synchronous counters avoid ripple, run faster, and give glitch-free outputs, but require extra gates and design effort. A 3-bit Gray code counter using D flip-flops follows 000,001,011,010,110,111,101,100. The D inputs are D2 = Q2 Q0 + Q1 Q0', D1 = Q2' Q0 + Q1 Q0', D0 = Q2 XNOR Q1.

## Answer

#### Synchronous over asynchronous counter
**Advantages**
- All flip-flops change together, so the total delay is one flip-flop delay plus one gate delay; the counter can run at a much higher clock frequency.
- No ripple, so there are no temporary false states and no glitches when outputs are decoded.
- Any count sequence (Gray, BCD, arbitrary) can be designed directly from the state table.
- Maximum frequency does not fall as more stages are added (with parallel carry).

**Disadvantages**
- Needs extra combinational logic (AND gates) for each stage, so the circuit is more complex and costlier.
- The clock drives every flip-flop, so the clock line has a larger load.
- Design takes more effort (excitation table, K-maps).

#### Design: 3-bit synchronous Gray code counter (D flip-flops)
Sequence: 000 → 001 → 011 → 010 → 110 → 111 → 101 → 100 → 000. 8 states, so 3 D flip-flops with a common clock. For a D flip-flop, $D = Q^+$, so the next-state columns give the D inputs directly.

| Present Q2Q1Q0 | Next Q2Q1Q0 | D2 | D1 | D0 |
|---|---|---|---|---|
| 000 | 001 | 0 | 0 | 1 |
| 001 | 011 | 0 | 1 | 1 |
| 011 | 010 | 0 | 1 | 0 |
| 010 | 110 | 1 | 1 | 0 |
| 110 | 111 | 1 | 1 | 1 |
| 111 | 101 | 1 | 0 | 1 |
| 101 | 100 | 1 | 0 | 0 |
| 100 | 000 | 0 | 0 | 0 |

**K-maps**

| D0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 1 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |

| D1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 1 |

| D2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 |

**Equations**
$$
\begin{aligned} D_2 &= Q_2Q_0 + Q_1\overline{Q_0} \\ D_1 &= \overline{Q_2}Q_0 + Q_1\overline{Q_0} \\ D_0 &= Q_2Q_1 + \overline{Q_2}\overline{Q_1} = \overline{Q_2 \oplus Q_1} \end{aligned}
$$

**Circuit**
```text
   +-----+       +-----+       +-----+
D0>|D   Q|-Q0 D1>|D   Q|-Q1 D2>|D   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
   |     |       |     |       |     |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
D2 = Q2.Q0 + Q1.Q0'
D1 = Q2'.Q0 + Q1.Q0'
D0 = XNOR(Q2, Q1)
```

**Timing diagram**
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Cnt  000  001 011 010 110 111 101 100 000
```
Only one output changes per clock, as required by the Gray code.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why can a synchronous counter run at a higher clock frequency than an asynchronous one?
   A. It has fewer flip-flops
   B. All flip-flops change together, so total delay is one flip-flop plus one gate delay
   C. It uses a lower supply voltage
   D. Its clock is divided internally
   Answer: B. No ripple means delay does not add stage by stage, so the maximum frequency is higher. (Key point: Speed advantage)

2. Which is a disadvantage of a synchronous counter?
   A. It produces glitches when decoded
   B. It needs extra combinational gates per stage, so it is more complex and costly
   C. It cannot count in Gray code
   D. Its maximum frequency drops as stages are added
   Answer: B. Synchronous counters need AND gates and more design effort; they do not ripple or glitch. (Key point: Disadvantage)

3. For a D flip-flop design of a counter, how are D inputs obtained?
   A. D = present state
   B. D = next state (D = Q+)
   C. D = complement of next state
   D. D = Q xor Q+
   Answer: B. For a D flip-flop Q+ = D, so the next-state columns give the D inputs directly. (Key point: D flip-flop design)

4. What is D0 for the 3-bit Gray counter?
   A. Q2 xor Q1
   B. XNOR of Q2 and Q1, i.e. Q2Q1 + Q2'Q1'
   C. Q2 + Q1
   D. Q2Q1'
   Answer: B. D0 is 1 in states 000, 001, 110, 111 where Q2 = Q1, so D0 = XNOR(Q2, Q1). (Key point: Gray code equations)

5. What property of the output sequence shows it is Gray code?
   A. Each output toggles every clock
   B. Only one output bit changes per clock
   C. Outputs count in binary order
   D. All outputs change together every clock
   Answer: B. In Gray code successive states differ in exactly one bit. (Key point: Gray property)

## Related in Digital Logic

- [Sync vs async; 3-bit synchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-down-counter-3bit) — Digital Logic, chapter 8
- [Sync vs async; 3-bit synchronous up counter (T)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-up-counter-3bit-t) — Digital Logic, chapter 8
- [3-bit Gray code synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Agray-code-sync-counter-3bit) — Digital Logic, chapter 8, asked 2×
- [Sync vs async; MOD-10 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-synchronous-counter) — Digital Logic, chapter 8, asked 2×
- [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8
- [Sync vs async; mod-12 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod12-synchronous-counter) — Digital Logic, chapter 8, asked 3×

## Related in other subjects

- [Transmission channels; sync vs async](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Atransmission-modes) — Data Communication, chapter 1
- [Multiplexing; synchronous vs asynchronous TDM](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Amux-compare-sync-async-tdm) — Data Communication, chapter 6, asked 6×
- [Synchronous vs asynchronous serial transmission](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-serial) — Microprocessor, chapter 4, asked 3×
- [Synchronous vs asynchronous transmission](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Async-vs-async) — Instrumentation II, chapter 3