--- title: "Half adder/subtractor; 1's and 2's complement subtraction" subject: "Digital Logic" chapter: 5 key: "semester_3/digital_logic:half-adder-subtractor-complement" source: https://www.bctengineer.com/q/semester_3/digital_logic/half-adder-subtractor-complement site: BCT Engineering --- # Half adder/subtractor; 1's and 2's complement subtraction Digital Logic · Chapter 5: Arithmetic Circuits - Asked in: 2081 Bhadra, 5+4 marks - Video: [Binary Subtraction | 1's | 2's | Complement | Digital logic design | Digital Electronics | STLD | CO](https://www.youtube.com/watch?v=TCGuxRbXU2Q) — Sudhakar Atchala - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/half-adder-subtractor-complement - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-5 ## Question Design half adder and half subtractor in a single circuit. Perform following operation: a) (47)₁₀ - (26)₁₀ subtraction using 2's complement method. b) (10010)₂ - (10011)₂ using 1's complement method. ## Short answer One XOR gate gives sum and difference S=D=A⊕B; carry C=AB, borrow Bo=A'B using two AND and one NOT. (a) 47-26: 47=00101111, 2's comp of 26=11100110; sum=1 00010101, discard end carry, result = 21. (b) 10010-10011: 1's comp of 10011=01100; sum=11110, no end-around carry, result = -00001 = -1. ## Answer #### Half adder and half subtractor in one circuit Inputs $A$, $B$. Outputs: sum $S$, carry $C$, difference $D$, borrow $B_o$ ($A - B$). | A | B | S | C | D | $B_o$ | |---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 1 | 1 | | 1 | 0 | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 1 | 0 | 0 | $$ S = D = A \oplus B, \qquad C = AB, \qquad B_o = A'B $$ The sum and difference are the same function, so **one XOR gate** serves both. Add one AND gate for $C$ and one NOT plus one AND gate for $B_o$. ```text A --+---------------[XOR]------> S (= D) B --|--+------------[ ] | | +--|------------[AND]------> C | +------------[ ] | | +--|--[NOT]--A'-[AND]------> Bo +------------[ ] ``` Total: 1 XOR, 2 AND, 1 NOT. (If one output pair with a mode input $M$ is preferred: $S/D = A \oplus B$, $C/B_o = (A \oplus M)B$, giving carry when $M=0$ and borrow when $M=1$.) #### a) (47)₁₀ − (26)₁₀ by 2's complement (8-bit) $$ \begin{aligned} 47 &= 0010\,1111 \\ 26 &= 0001\,1010 \\ \text{2's complement of } 26 &= 1110\,0101 + 1 = 1110\,0110 \end{aligned} $$ ```text 0010 1111 (+47) + 1110 0110 (-26) ----------- 1 0001 0101 ``` An end carry occurs: discard it. The result is positive. **Answer:** $0001\,0101_2 = 16 + 4 + 1 = 21$. Check: $47 - 26 = 21$. #### b) (10010)₂ − (10011)₂ by 1's complement $$ \text{1's complement of } 10011 = 01100 $$ ```text 10010 + 01100 ------- 11110 (no end-around carry) ``` No end carry, so the result is negative; take its 1's complement: $$ \overline{11110} = 00001 $$ **Answer:** $(10010)_2 - (10011)_2 = -(00001)_2 = -1$. Check: $18 - 19 = -1$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which gate is shared by half adder and half subtractor? A. XOR gives both S and D B. AND C. NOT D. NOR Answer: A. S = D = A xor B. (Key point: Shared gate) 2. What is the half subtractor borrow Bo (A - B)? A. AB' B. A'B C. AB D. A xor B Answer: B. Borrow occurs when A = 0 and B = 1. (Key point: Borrow) 3. What is 47 - 26 by 2's complement, and what happens to the end carry? A. 21; the end carry is added back B. -21; end carry kept C. 21; the end carry is discarded D. 73; no carry Answer: C. An end carry means a positive result, which is dropped. (Key point: 47-26) 4. (10010)2 - (10011)2 by 1's complement gives 11110 with no end carry. The answer is A. +1 B. -30 C. +30 D. -1 Answer: D. No end carry means negative; the complement 00001 gives -1. (Key point: 1's complement) ## Related in Digital Logic - [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5 - [De Morgan's theorem and (-47+27) by 2's complement](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-twos-complement-addition) — Digital Logic, chapter 2 - [FFH AND C0H; (16)₁₀ − (26)₁₀ by 2's complement](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahex-and-twos-complement-subtract) — Digital Logic, chapter 5 - [Full adder using decoder; (57−43) by 2's complement](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-decoder-subtract) — Digital Logic, chapter 4 - [Half subtractor using HDL](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahalf-subtractor-hdl) — Digital Logic, chapter 2 - [Full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-half-subtractors) — Digital Logic, chapter 5 ## Related in other subjects - [2's complement subtraction; AND using NOR](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Atwo-complement-111-110-nor-and) — Basic Electronics Engineering, chapter 6 - [VHDL PROCESS; full adder with half adders](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-process-full-adder) — Embedded System, chapter 9 - [Single-phase half-wave thyristor rectifier, R load](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_electronics%3Ahalf-wave-thyristor-r-load-rms) — Power Electronics, chapter 2 - [Chopper definition; single-phase half bridge inverter](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Achopper-half-bridge-inverter) — Advanced Electronics, chapter 7