---
title: "Half subtractor using HDL"
subject: "Digital Logic"
chapter: 2
key: "semester_3/digital_logic:half-subtractor-hdl"
source: https://www.bctengineer.com/q/semester_3/digital_logic/half-subtractor-hdl
site: BCT Engineering
---

# Half subtractor using HDL

Digital Logic · Chapter 2: Digital Logic

- Asked in: 2075 Asoj, 4 marks
- Video: [Implementation of Half Subtractor Using NHDL Code Considering Dataflow Modeling | VHDL in EXTC](https://www.youtube.com/watch?v=5Tyn-6xeLGY) — Ekeeda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/half-subtractor-hdl
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-2

## Question

Design half subtractor circuit using HDL.

## Short answer

A half subtractor subtracts B from A, giving difference D = A XOR B and borrow Bo = A'B. In Verilog dataflow: assign D = A ^ B; assign Bo = ~A & B; gate-level uses xor and and primitives.

## Answer

A **half subtractor** subtracts one bit B from another bit A and gives a **Difference (D)** and a **Borrow (Bo)**.

| A | B | D | Bo |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |

$$
D = A \oplus B, \qquad B_o = \bar A B
$$

```text
 A --+--[XOR]------------ D
 B --+--|
 A --[NOT]--[AND]-------- Bo
 B ---------|
```

**Verilog HDL description**

```verilog
// Half subtractor: gate-level (structural) model
module half_sub_gate (input A, B, output D, Bo);
  wire An;              // complement of A
  xor g1 (D, A, B);     // D  = A XOR B
  not g2 (An, A);       // An = A'
  and g3 (Bo, An, B);   // Bo = A'B
endmodule

// Same circuit: dataflow model
module half_sub_df (input A, B, output D, Bo);
  assign D  = A ^ B;    // difference
  assign Bo = ~A & B;   // borrow
endmodule
```

**Test bench (simulation)**

```verilog
module tb;
  reg A, B; wire D, Bo;
  half_sub_df uut (A, B, D, Bo);
  initial begin
    $monitor("A=%b B=%b D=%b Bo=%b", A, B, D, Bo);
    {A,B} = 2'b00; #10 {A,B} = 2'b01;
    #10 {A,B} = 2'b10; #10 {A,B} = 2'b11;
    #10 $finish;
  end
endmodule
```

Simulation output matches the truth table, e.g. `A=0 B=1 D=1 Bo=1` and `A=1 B=1 D=0 Bo=0`.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Half subtractor difference D =
   A. A and B
   B. A'B
   C. A xor B
   D. A + B
   Answer: C. D = 1 when inputs differ. (Key point: Difference)

2. Borrow Bo =
   A. AB'
   B. AB
   C. A'B
   D. A xor B
   Answer: C. Borrow when subtracting 1 from 0. (Key point: Borrow)

3. Which is borrow in dataflow Verilog?
   A. assign Bo = A & ~B;
   B. assign Bo = ~A & B;
   C. assign Bo = A ^ B;
   D. assign Bo = A | B;
   Answer: B. Matches A'B. (Key point: Verilog dataflow)

4. Purpose?
   A. Apply all inputs and check outputs against truth table
   B. Synthesize the chip
   C. Replace the module
   D. Remove outputs
   Answer: A. $monitor prints each case. (Key point: Test bench)

## Related in Digital Logic

- [Half adder/subtractor; 1's and 2's complement subtraction](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahalf-adder-subtractor-complement) — Digital Logic, chapter 5
- [Full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-half-subtractors) — Digital Logic, chapter 5
- [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5
- [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4
- [HDL and 2-to-4 decoder in HDL](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahdl-2to4-decoder) — Digital Logic, chapter 2
- [Full subtractor using a 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-1to4-demux) — Digital Logic, chapter 4, asked 6×

## Related in other subjects

- [Equivalent circuit and half-load efficiency of 50 kVA transformer](https://www.bctengineer.com/question.md?key=semester_4%2Felectrical_machines_i%3A50kva-2500-250-test-secondary-half) — Electrical Machines I, chapter 2
- [Design: 250 m head plant, 66 kV double circuit](https://www.bctengineer.com/question.md?key=semester_8%2Fpower_plant_design%3Adesign-2071-250m-0-92mh) — Power Plant Design, chapter 4, asked 13×
- [Establishing requirements for circuit design](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Areq-to-design) — Instrumentation II, chapter 7, asked 4×
- [Technical dilemmas in circuit design](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adesign-dilemmas) — Instrumentation II, chapter 7