--- title: "Hazards in asynchronous design; 2-bit comparator" subject: "Digital Logic" chapter: 4 key: "semester_3/digital_logic:hazards-2bit-comparator" source: https://www.bctengineer.com/q/semester_3/digital_logic/hazards-2bit-comparator site: BCT Engineering --- # Hazards in asynchronous design; 2-bit comparator Digital Logic · Chapter 4: Data Processing Circuits - Asked in: 2075 Asoj, 2+4 marks - Video: [Hazards | Types of Hazards | Static Hazards | Dynamic Hazards | Essential Hazards | Tamil |](https://www.youtube.com/watch?v=irrt7C0Zbdg) — Learn ECE Easy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/hazards-2bit-comparator - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4 ## Question What is the role of hazards in asynchronous circuit design? Explain two bit magnitude comparator with necessary diagrams. ## Short answer Hazards cause unwanted glitches that can lead to wrong states in asynchronous circuits, so they must be removed. A 2-bit magnitude comparator gives E = (A1⊙B1)(A0⊙B0), G = A1B1' + (A1⊙B1)A0B0', L = A1'B1 + (A1⊙B1)A0'B0. ## Answer #### Role of hazards in asynchronous circuit design A **hazard** is an unwanted momentary pulse (glitch) at a circuit output caused by unequal propagation delays along different paths when an input changes. Types: static-1 (output should stay 1 but dips to 0), static-0, and dynamic hazards; essential hazards come from feedback delays. In **asynchronous** circuits there is no clock to wait until signals settle, and outputs are fed back as state variables. A glitch can therefore be taken as a real change and drive the circuit into a **wrong stable state**, causing malfunction. So hazards must be removed, e.g. by adding redundant (consensus) terms in the K-map so that every pair of adjacent 1s is covered by a common group, and by careful delay control. #### Two-bit magnitude comparator It compares $A = A_1A_0$ and $B = B_1B_0$ and gives three outputs: $G$ ($A > B$), $E$ ($A = B$) and $L$ ($A < B$). Let $x_1 = A_1 \odot B_1$ and $x_0 = A_0 \odot B_0$ (bit-equal signals). Compare the MSBs first; only if they are equal, compare the LSBs: $$ \begin{aligned} E &= x_1 x_0 \\ G &= A_1B_1' + x_1A_0B_0' \\ L &= A_1'B_1 + x_1A_0'B_0 \end{aligned} $$ From K-maps the same functions in plain SOP are: $$ G = A_1B_1' + A_0B_1'B_0' + A_1A_0B_0', \quad L = A_1'B_1 + A_0'B_1B_0 + A_1'A_0'B_0 $$ Partial truth table: | $A_1A_0$ | $B_1B_0$ | G | E | L | |---|---|---|---|---| | 10 | 01 | 1 | 0 | 0 | | 01 | 01 | 0 | 1 | 0 | | 01 | 11 | 0 | 0 | 1 | | 11 | 10 | 1 | 0 | 0 | ```text A1,B1 --[XNOR]-- x1 A0,B0 --[XNOR]-- x0 x1, x0 ------------------[AND]------------ E A1,B1' ---[AND]---+ x1,A0,B0' [AND]---+------[OR]------------- G A1',B1 ---[AND]---+ x1,A0',B0 [AND]---+------[OR]------------- L ``` Example: $A = 11$, $B = 10$: $x_1 = 1$, $A_0B_0' = 1$, so $G = 1$. All 16 input combinations were verified. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What causes a hazard (glitch) in a combinational circuit? A. A wrong truth table B. Unequal propagation delays along different paths when an input changes C. Excess supply voltage D. Too many inputs Answer: B. Signals racing through paths of different delay can produce a momentary wrong pulse at the output. (Key point: Cause of hazards) 2. Why are hazards especially harmful in asynchronous circuits? A. They make the circuit slower only B. With no clock and feedback, a glitch can drive the circuit into a wrong stable state C. They damage the gates D. They change the number of outputs Answer: B. There is no clock to wait for settling, so a glitch fed back as state can be taken as a real change. (Key point: Why hazards matter in asynchronous circuits) 3. How is a static-1 hazard removed using the K-map? A. Remove all groups B. Add a redundant (consensus) group covering each pair of adjacent 1s C. Use more inverters D. Convert to POS only Answer: B. A redundant group ensures every adjacent pair of 1s is covered by a common term. (Key point: Hazard removal) 4. In the 2-bit comparator, which expression gives G (A > B)? A. A1B1' + x1 A0 B0' B. A1'B1 + x1 A0' B0 C. x1 x0 D. A1B1 + A0B0 Answer: A. A > B if the MSB of A is larger, or the MSBs are equal (x1) and the LSB of A is larger. (Key point: Comparator equations) ## Related in Digital Logic - [2-bit magnitude comparator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amagnitude-comparator-2bit) — Digital Logic, chapter 4, asked 6× - [3-bit magnitude comparator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amagnitude-comparator-3bit) — Digital Logic, chapter 4, asked 6× - [2-bit equality comparator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aequality-comparator-2bit) — Digital Logic, chapter 4, asked 2× - [4-bit equality comparator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aequality-comparator-4bit) — Digital Logic, chapter 4, asked 2× - [3-bit asynchronous up/down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-up-down-counter-3bit) — Digital Logic, chapter 8, asked 2× - [4-bit asynchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-down-counter-4bit) — Digital Logic, chapter 8 ## Related in other subjects - [Two-layer sand, stress diagrams (3 m, 4 m)](https://www.bctengineer.com/question.md?key=semester_4%2Fsoil_mechanics%3Atwo-layer-sand-stress-diagrams) — Soil Mechanics, chapter 6 - [Create classes from design class diagrams](https://www.bctengineer.com/question.md?key=semester_6%2Fobject_oriented_analysis_and_design%3Aclasses-from-design-class-diagram) — Object Oriented Analysis and Design, chapter 4, asked 2× - [8085 ALP: compare two tables of 16-bit data](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-compare-tables-1ffffh) — Microprocessor, chapter 2 - [C program: sum of two 8-bit BCD numbers](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-bcd-sum-c) — Embedded System, chapter 9