--- title: "Hazard types and hazard cover in K-maps" subject: "Digital Logic" chapter: 3 key: "semester_3/digital_logic:hazards-hazard-cover" source: https://www.bctengineer.com/q/semester_3/digital_logic/hazards-hazard-cover site: BCT Engineering --- # Hazard types and hazard cover in K-maps Digital Logic · Chapter 3: Combinational Logic Circuits - Asked in: 2076 Chaitra, 1+4 marks - Video: [Finding and Eliminationg Hazards in the circuit using K-Map](https://www.youtube.com/watch?v=fUTCtn_b4qs) — Electrical Engineering Authority - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/hazards-hazard-cover - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3 ## Question What is hazard? Explain types of hazards with hazard cover techniques used in K-map simplification. ## Short answer A hazard is a momentary glitch caused by unequal propagation delays. Static-1 hazard: output should stay 1 but briefly goes to 0 in SOP circuits; static-0: stays 0 but glitches to 1 in POS; dynamic: multiple transitions. Hazard cover: add a redundant prime implicant covering adjacent 1s not in the same group (e.g., add BC to F=AB+A'C) to eliminate static hazards. ## Answer A **hazard** is an unwanted momentary pulse (glitch) at the output of a combinational circuit, caused by unequal propagation delays along different paths when an input changes. The steady-state output is correct, but the transient is wrong; in sequential systems such glitches can trigger flip-flops falsely. #### Types of hazards | Type | Expected output | Actual output | Usually found in | |---|---|---|---| | Static-1 | stays 1 | $1 \to 0 \to 1$ | SOP (AND-OR) circuits | | Static-0 | stays 0 | $0 \to 1 \to 0$ | POS (OR-AND) circuits | | Dynamic | one change, $0 \to 1$ | $0 \to 1 \to 0 \to 1$ | multi-level circuits | - **Static hazard:** the output should not change, but it briefly changes and returns. - **Dynamic hazard:** the output should change once but changes several times, because the changing input reaches the output by three or more paths of different delay. #### Hazard cover in K-maps (example) $$ F = AB + \overline{A}C $$ ```text BC A 00 01 11 10 +---+---+---+---+ 0 | 0 | 1 | 1 | 0 | A'C = cells 1, 3 +---+---+---+---+ 1 | 0 | 0 | 1 | 1 | AB = cells 7, 6 +---+---+---+---+ ``` Cells 3 (011) and 7 (111) are adjacent 1s but lie in different groups. With $B = C = 1$, F should stay 1 while A changes. When A goes $1 \to 0$, the term $AB$ falls at once but $\overline{A}C$ rises only after the inverter delay, so F momentarily becomes 0: a static-1 hazard. **Hazard cover technique:** add a redundant group that covers every pair of adjacent 1s not already in a common group. Here the extra group is cells 3 and 7, i.e. the consensus term $BC$: $$ F = AB + \overline{A}C + BC $$ While A changes with $B = C = 1$, $BC = 1$ keeps F at 1, so the glitch disappears. The function is unchanged (consensus theorem: $AB + \overline{A}C + BC = AB + \overline{A}C$), only the circuit gains one gate. **Rules** 1. For SOP circuits: every two adjacent 1-cells must be covered by at least one common prime implicant (removes static-1 hazards). 2. For POS circuits: every two adjacent 0-cells must be covered by a common sum term (removes static-0 hazards). 3. A two-level circuit built with full hazard cover is also free of dynamic hazards; dynamic hazards are avoided by not using multi-level paths for the same variable. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What causes a hazard in a combinational circuit? A. Wrong steady-state logic design B. Unequal propagation delays along different paths when an input changes C. Too many gates in the circuit D. Supply voltage drop Answer: B. Different path delays make signals arrive at different times, causing a momentary glitch even though the final output is correct. (Key point: Cause of hazard) 2. What is a static-1 hazard? A. Output should stay 0 but briefly goes to 1 B. Output should stay 1 but briefly goes 1 → 0 → 1 C. Output changes 0 → 1 → 0 → 1 D. Output stays stuck at 1 Answer: B. A static-1 hazard is a glitch to 0 when the output should remain 1; it is typical of SOP circuits. (Key point: Static-1 hazard) 3. For F = AB + A'C, which redundant term covers the hazard when A changes with B = C = 1? A. B'C' B. A'B C. BC D. AC Answer: C. Cells 3 and 7 are adjacent 1s in different groups; adding their common group, the consensus term BC, holds F at 1. (Key point: Hazard cover) 4. How does a dynamic hazard differ from a static hazard? A. The output changes several times when it should change once, through three or more paths B. It only occurs in POS circuits C. The output stays constant but glitches D. It occurs only in sequential circuits Answer: A. A dynamic hazard gives 0 → 1 → 0 → 1 for one intended change, due to the input reaching the output by three or more paths of different delay. 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