---
title: "HDL and 2-to-4 decoder in HDL"
subject: "Digital Logic"
chapter: 2
key: "semester_3/digital_logic:hdl-2to4-decoder"
source: https://www.bctengineer.com/q/semester_3/digital_logic/hdl-2to4-decoder
site: BCT Engineering
---

# HDL and 2-to-4 decoder in HDL

Digital Logic · Chapter 2: Digital Logic

- Asked in: 2068 Baisakh, 2+3 marks
- Video: [Design a Verilog Code for 2 to 4 Decoder | VLSI Design | S VIJAY MURUGAN](https://www.youtube.com/watch?v=vAUN-jxgUok) — LEARN THOUGHT
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/hdl-2to4-decoder
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-2

## Question

What do you mean by HDL? Design a 2 to 4 line decoder circuit using HDL.

## Short answer

HDL is a language to describe digital hardware, enabling simulation and synthesis. A 2-to-4 decoder with inputs A1,A0 and enable E can be designed in Verilog using continuous assignments: D0 = E & ~A1 & ~A0, D1 = E & ~A1 & A0, D2 = E & A1 & ~A0, D3 = E & A1 & A0.

## Answer

#### HDL
A **Hardware Description Language (HDL)** is a computer language used to describe the structure and behaviour of digital circuits in text form. The description can be **simulated** to check the design and **synthesised** into gates for an FPGA, CPLD or ASIC. Common HDLs are **Verilog** and **VHDL**. A design can be written at gate level (structural), dataflow (`assign` equations) or behavioural (`always` blocks) level.

#### 2-to-4 line decoder
Inputs A1 A0 and enable E; exactly one output goes HIGH for each input code when E = 1.

| E | A1 | A0 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|
| 0 | x | x | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 |

$D_0 = E\bar A_1 \bar A_0$, $D_1 = E\bar A_1 A_0$, $D_2 = E A_1 \bar A_0$, $D_3 = E A_1 A_0$

**Verilog (dataflow model)**

```verilog
module decoder2to4 (input A1, A0, E,
                   output D0, D1, D2, D3);
  assign D0 = E & ~A1 & ~A0; // 00
  assign D1 = E & ~A1 &  A0; // 01
  assign D2 = E &  A1 & ~A0; // 10
  assign D3 = E &  A1 &  A0; // 11
endmodule
```

**Verilog (gate-level model)**

```verilog
module decoder2to4_g (input A1, A0, E,
                     output D0, D1, D2, D3);
  wire n1, n0;
  not (n1, A1);           // A1'
  not (n0, A0);           // A0'
  and (D0, E, n1, n0);
  and (D1, E, n1, A0);
  and (D2, E, A1, n0);
  and (D3, E, A1, A0);
endmodule
```

With E = 1 and A1A0 = 10, simulation gives D3D2D1D0 = 0100.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is an HDL?
   A. A programme that draws PCBs
   B. A type of flip-flop
   C. A memory chip
   D. A text language describing structure and behaviour of digital circuits
   Answer: D. HDLs like Verilog and VHDL can be simulated and synthesised. (Key point: HDL meaning)

2. For a 2-to-4 decoder with E=1, how many outputs are HIGH?
   A. Exactly one
   B. Two
   C. All four
   D. None
   Answer: A. Each input code activates exactly one output line. (Key point: Decoder output)

3. Which equation gives D2 of the decoder?
   A. E & ~A1 & A0
   B. E & A1 & ~A0
   C. E & A1 & A0
   D. E & ~A1 & ~A0
   Answer: B. D2 corresponds to code 10, so A1=1, A0=0. (Key point: Equation)

4. With E = 0, the outputs are:
   A. D0 = 1 only
   B. Follow A1A0 anyway
   C. All 0
   D. High impedance 1s
   Answer: C. The enable gates every output, so all are 0 when E=0. (Key point: Enable)

## Related in Digital Logic

- [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4
- [Half subtractor using HDL](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahalf-subtractor-hdl) — Digital Logic, chapter 2
- [Decoder; 2-to-4 decoder as a full adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adecoder-2to4-full-adder) — Digital Logic, chapter 4
- [5×32 decoder using 3×8 decoders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adecoder-5x32-from-3x8) — Digital Logic, chapter 4, asked 3×
- [Seven-segment decoder "b" segment](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ab-segment-seven-segment) — Digital Logic, chapter 4, asked 2×
- [Full subtractor using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-2x4-decoder) — Digital Logic, chapter 4, asked 4×

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