--- title: "JK characteristic equation and toggle mode" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:jk-characteristic-toggle" source: https://www.bctengineer.com/q/semester_3/digital_logic/jk-characteristic-toggle site: BCT Engineering --- # JK characteristic equation and toggle mode Digital Logic · Chapter 6: Flip Flops - Asked in: 2073 Shrawan, 3+2+2 marks - Video: [Truth Table, Characteristic Table and Excitation Table for JK flip flop](https://www.youtube.com/watch?v=lnQD2_M9uDI) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/jk-characteristic-toggle - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Derive characteristic equation of a JK flip flop. How do you make it a toggle flip flop? Draw the input and output wave form of JK flip flop. ## Short answer The characteristic equation of a JK flip-flop is Q(n+1) = J Q(n)' + K' Q(n). To make a toggle flip-flop, connect J and K together to a common input T; then Q(n+1) = T XOR Q(n). The output toggles each clock when T=1. ## Answer #### Characteristic equation of J-K flip-flop The characteristic table lists the next state $Q_{n+1}$ for every combination of J, K and present state $Q_n$: | J | K | Q | Q+ | |---|---|---|---| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 0 | (J K = 00 hold, 01 reset, 10 set, 11 toggle.) Plotting $Q_{n+1}$ on a 3-variable K-map: ```text K-map for Q+ (rows Q, columns JK) Q\JK 00 01 11 10 0 0 0 1 1 1 1 0 0 1 Groups: J.Q' (row 0, cells 11,10) K'.Q (row 1, cells 00,10) ``` - Row Q = 0, columns JK = 11 and 10 give $J\,\overline{Q_n}$. - Row Q = 1, columns JK = 00 and 10 give $\overline{K}\,Q_n$. $$ Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n $$ #### Making a toggle (T) flip-flop Connect J and K together and call the common input T (or tie J = K = 1 for permanent toggling). ```text +---------+ T --+----| J Q |--- Q | | | | CLK|> JK | | | | +----| K Q' |--- Q' +---------+ ``` With J = K = T, the equation becomes $$ Q_{n+1} = T\,\overline{Q_n} + \overline{T}\,Q_n = T \oplus Q_n $$ so T = 0 holds the state and T = 1 toggles it at every clock edge (a divide-by-2 circuit when T = 1). #### Input and output waveforms (positive edge triggered, Q initially 0) ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| J ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾| K _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾| Q _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__ ``` | Edge | J | K | Q before | Q after | Action | |---|---|---|---|---|---| | 1 | 1 | 0 | 0 | 1 | Set | | 2 | 0 | 0 | 1 | 1 | Hold | | 3 | 1 | 1 | 1 | 0 | Toggle | | 4 | 1 | 1 | 0 | 1 | Toggle | | 5 | 0 | 1 | 1 | 0 | Reset | | 6 | 1 | 0 | 0 | 1 | Set | | 7 | 1 | 1 | 1 | 0 | Toggle | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the JK characteristic equation? A. Qn+1 = J' Qn + K Qn' B. Qn+1 = J K + Qn C. Qn+1 = J Qn + K Qn' D. Qn+1 = J Qn' + K' Qn Answer: D. The K-map groups are J.Q' and K'.Q. (Key point: Characteristic equation) 2. How is a JK flip-flop made into a toggle flip-flop? A. Connect J and K together as T B. Tie J = K = 0 C. Tie J = 0 and K = 1 D. Connect J to Q Answer: A. With J = K = T, Qn+1 = T XOR Qn: hold if T = 0, toggle if T = 1. (Key point: Toggle) 3. What happens with T = 1 at every clock edge? A. Q holds B. Q toggles, giving a divide-by-2 circuit C. Q sets D. Q resets Answer: B. Q changes once per clock, so its frequency is half that of the clock. (Key point: Divide by two) 4. In the waveform, at edge 3 with J = K = 1 and Q before = 1, what is Q after? A. Invalid B. 1 C. 0 D. Unchanged Answer: C. J=K=1 toggles, so Q goes from 1 to 0. (Key point: Waveform) ## Related in Digital Logic - [JK flip-flop characteristic and excitation tables](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-characteristic-excitation) — Digital Logic, chapter 6, asked 2× - [JK flip-flop with symbol, equation, state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-state-diagram) — Digital Logic, chapter 6 - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× - [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [T to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3At-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [Negative edge JK flip-flop; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-negative-edge-t-to-jk) — Digital Logic, chapter 6 ## Related in other subjects - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9 - [VHDL COMPONENT; JK flip-flop with PROCESS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-component-jk-ff) — Embedded System, chapter 9