---
title: "JK flip-flop with symbol, equation, state diagram"
subject: "Digital Logic"
chapter: 6
key: "semester_3/digital_logic:jk-flipflop-state-diagram"
source: https://www.bctengineer.com/q/semester_3/digital_logic/jk-flipflop-state-diagram
site: BCT Engineering
---

# JK flip-flop with symbol, equation, state diagram

Digital Logic · Chapter 6: Flip Flops

- Asked in: 2082 Baisakh, 8 marks
- Video: [JK Flip Flop: Circuit, Working, Truth Table, Characteristics Table & Excitation Table](https://www.youtube.com/watch?v=8trVtmPMSbY) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/jk-flipflop-state-diagram
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6

## Question

Explain the operation of J-K flip-flop with logic diagram, graphic symbol, characteristics table, characteristic equation and state diagram.

## Short answer

A JK flip-flop toggles when J=K=1, sets for J=1,K=0, resets for J=0,K=1, and holds for 00. Characteristic equation: Q+ = J Q' + K' Q. The state diagram has two states: 0→1 on 1x, 1→0 on x1; self-loops for 0: 0x, 1: x0.

## Answer

A **J-K flip-flop** is an improved S-R flip-flop: J acts like Set, K like Reset, and the input J = K = 1, which is invalid for S-R, makes the output **toggle**.

#### Logic diagram (clocked J-K using NAND gates)

```text
          +------+  S*  +------+
 J -------|      |----->|      |
 CLK -----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK -----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3-G4: cross-coupled NAND latch. Q' is fed
 back to G1 and Q to G2.
```

G1 gets J, CLK and Q'; G2 gets K, CLK and Q; G3-G4 form a NAND latch. In practice the clock is an edge (or master-slave) clock so that the output changes once per clock.

#### Graphic symbol

```text
      +---------+
 J ---| J     Q |--- Q
 CLK -|>        |
 K ---| K    Q' |--- Q'
      +---------+
 '>' = edge triggered (a bubble 'o>' means
 negative edge triggered)
```

#### Operation

- **J = 0, K = 0:** G1 = G2 = 1, latch holds: no change.
- **J = 0, K = 1:** G2 = 0 when Q = 1, latch resets: Q = 0.
- **J = 1, K = 0:** G1 = 0 when Q = 0, latch sets: Q = 1.
- **J = 1, K = 1:** only the gate with the 1 feedback fires, so the output toggles: Q+ = Q'.
- No clock: inputs ignored, output held.

#### Characteristic table

| J | K | Q | Q+ |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |

#### Characteristic equation

```text
K-map for Q+ (rows Q, columns JK)
Q\JK   00  01  11  10
 0      0   0   1   1
 1      1   0   0   1
 Groups: J.Q' (row 0, cells 11,10)
         K'.Q (row 1, cells 00,10)
```

$$
Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n
$$

#### State diagram

The flip-flop has two states, Q = 0 and Q = 1. Each arrow is labelled with the J K inputs that cause that transition at the clock edge (x = don't care):

```text
              JK = 1x
     +-------------------------+
     |                         v
  +-------+               +-------+
  | Q = 0 |               | Q = 1 |
  +-------+               +-------+
     ^                         |
     +-------------------------+
              JK = x1
 Self-loop on Q=0: JK = 0x (00 or 01)
 Self-loop on Q=1: JK = x0 (00 or 10)
```

- From 0: stays 0 for JK = 00 (hold) or 01 (reset); goes to 1 for 10 (set) or 11 (toggle).
- From 1: stays 1 for JK = 00 or 10; goes to 0 for 01 or 11.

These labels are exactly the excitation table: 0 to 1 needs J = 1, K = x; 1 to 0 needs J = x, K = 1.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does the J-K flip-flop do for J = K = 1, which is invalid for S-R?
   A. Holds its state
   B. Sets Q = 1
   C. Toggles: Q+ = Q'
   D. Resets Q = 0
   Answer: C. The J = K = 1 input makes the output toggle. (Key point: J=K=1 toggle)

2. Which is the characteristic equation read from the K-map groups?
   A. Q+ = J Q' + K' Q
   B. Q+ = J' Q + K Q'
   C. Q+ = J K + Q
   D. Q+ = J Q + K Q'
   Answer: A. The groups are J.Q' and K'.Q. (Key point: Characteristic equation)

3. Which J K inputs cause the transition from Q = 0 to Q = 1?
   A. JK = x1
   B. JK = 0x
   C. JK = 1x
   D. JK = x0
   Answer: C. From 0 to 1 needs J = 1, K = don't care (set or toggle). (Key point: State diagram 0 to 1)

4. Which inputs cause the transition from Q = 1 to Q = 0, and which keep it at 1?
   A. Go to 0 for JK = x1; stay at 1 for JK = x0
   B. Go to 0 for JK = x0; stay at 1 for JK = x1
   C. Go to 0 for JK = 1x; stay at 1 for JK = 0x
   D. Go to 0 only for JK = 11
   Answer: A. From 1: reset (01) or toggle (11) go to 0, so K = 1; JK = 00 or 10 keeps 1. (Key point: State diagram 1 to 0)

## Related in Digital Logic

- [JK flip-flop characteristic and excitation tables](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-characteristic-excitation) — Digital Logic, chapter 6, asked 2×
- [SR flip-flop diagram, excitation table, equation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-flipflop-diagram-equation) — Digital Logic, chapter 6
- [JK flip-flop with tables and timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-timing-diagram) — Digital Logic, chapter 6, asked 2×
- [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6
- [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3×
- [Positive edge SR flip-flop and its state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-positive-edge-state-diagram) — Digital Logic, chapter 6

## Related in other subjects

- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6
- [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6×
- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
