--- title: "JK flip-flop with tables and timing diagram" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:jk-flipflop-timing-diagram" source: https://www.bctengineer.com/q/semester_3/digital_logic/jk-flipflop-timing-diagram site: BCT Engineering --- # JK flip-flop with tables and timing diagram Digital Logic · Chapter 6: Flip Flops - Asked in: 2076 Asoj - Video: [Introduction to JK flip flop](https://www.youtube.com/watch?v=j6krFp511HA) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/jk-flipflop-timing-diagram - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Explain the operation of J-K flip flop with its logical diagram, characteristics table, characteristics equation, excitation table and timing diagram. ## Short answer A J-K flip-flop is a clocked bistable with J (set) and K (reset). J=K=1 toggles; J=K=0 holds. Characteristic equation: Q+ = J·Q' + K'·Q. Excitation: 0→1 needs J=1, K=x; 1→0 needs J=x, K=1. ## Answer A **J-K flip-flop** is a clocked flip-flop with inputs J (set) and K (reset). Unlike the S-R flip-flop, the input J = K = 1 is allowed and makes the output toggle. #### Logic diagram Edge-triggered J-K using NAND gates; CLK* is a narrow pulse made at each rising edge of CLK by an edge detector (CLK ANDed with its delayed complement): ```text +------+ S* +------+ J -------| |----->| | CLK* ----| NAND | | NAND |-----> Q Q' ------| G1 | Q'->| G3 | +------+ +------+ +------+ R* +------+ K -------| |----->| | CLK* ----| NAND | | NAND |-----> Q' Q ------| G2 | Q-->| G4 | +------+ +------+ G3 and G4 are cross-coupled (NAND latch). Q' is fed back to G1, Q is fed back to G2. ``` ```text +---------+ J ---| J Q |--- Q CLK -|> | K ---| K Q' |--- Q' +---------+ '>' = edge triggered (a bubble 'o>' means negative edge triggered) ``` **Operation** - J = K = 0: G1, G2 disabled, latch holds the state. - J = 0, K = 1: at the edge G2 gives 0 (if Q = 1) and resets: Q = 0. - J = 1, K = 0: at the edge G1 gives 0 (if Q = 0) and sets: Q = 1. - J = K = 1: the gate with the 1 feedback fires, the output toggles once per edge. #### Characteristic table | J | K | Q | Q+ | |---|---|---|---| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 0 | #### Characteristic equation ```text K-map for Q+ (rows Q, columns JK) Q\JK 00 01 11 10 0 0 0 1 1 1 1 0 0 1 Groups: J.Q' (row 0, cells 11,10) K'.Q (row 1, cells 00,10) ``` $$ Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n $$ #### Excitation table | Q | Q+ | J | K | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | x | | 1 | 0 | x | 1 | | 1 | 1 | x | 0 | #### Timing diagram (positive edge triggered, Q initially 0) ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| J ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾| K _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾| Q _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__ ``` | Edge | J | K | Q before | Q after | Action | |---|---|---|---|---|---| | 1 | 1 | 0 | 0 | 1 | Set | | 2 | 0 | 0 | 1 | 1 | Hold | | 3 | 1 | 1 | 1 | 0 | Toggle | | 4 | 1 | 1 | 0 | 1 | Toggle | | 5 | 0 | 1 | 1 | 0 | Reset | | 6 | 1 | 0 | 0 | 1 | Set | | 7 | 1 | 1 | 1 | 0 | Toggle | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. At an edge with J = K = 1 and Q = 1, what is Q after the edge? A. 1 B. 0 C. Undefined D. Unchanged Answer: B. J = K = 1 toggles the output, so Q goes from 1 to 0. (Key point: J=K=1 toggle) 2. What J and K are needed for the change Q = 1 to Q+ = 0? A. J = 1, K = x B. J = x, K = 0 C. J = 0, K = 0 D. J = x, K = 1 Answer: D. For 1 to 0, J is don't care and K = 1. (Key point: Excitation table) 3. What happens at an edge with J = 0, K = 0? A. Q toggles B. Q resets C. Q holds its state D. Q sets Answer: C. G1 and G2 are disabled so the latch holds. (Key point: Edge-triggered action) 4. In the timing diagram, edge 5 has J = 0, K = 1 with Q = 1. What happens? A. Q stays 1 B. Q resets to 0 C. Q toggles to 0 because J = K D. Q becomes undefined Answer: B. J = 0, K = 1 is the reset action, so Q becomes 0. (Key point: Timing example) ## Close variants set in other exams - [SR flip-flop with tables, equation, timing](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-flipflop-full-description) — Digital Logic, chapter 6, asked 2× ## Related in Digital Logic - [JK flip-flop characteristic and excitation tables](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-characteristic-excitation) — Digital Logic, chapter 6, asked 2× - [SR flip-flop diagram, excitation table, equation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-flipflop-diagram-equation) — Digital Logic, chapter 6 - [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6 - [JK flip-flop with symbol, equation, state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-state-diagram) — Digital Logic, chapter 6 - [D flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ad-flipflop-excitation) — Digital Logic, chapter 6 - [JK over SR advantages; D flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-over-sr-d-flipflop) — Digital Logic, chapter 6 ## Related in other subjects - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6× - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×