--- title: "Negative edge JK flip-flop; T to JK conversion" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:jk-negative-edge-t-to-jk" source: https://www.bctengineer.com/q/semester_3/digital_logic/jk-negative-edge-t-to-jk site: BCT Engineering --- # Negative edge JK flip-flop; T to JK conversion Digital Logic · Chapter 6: Flip Flops - Asked in: 2081 Bhadra, 3+5 marks - Video: [Lec - 40: T flip flop to JK flip flop Conversion | Digital Logic](https://www.youtube.com/watch?v=2M4tZaPiWj4) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/jk-negative-edge-t-to-jk - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Explain briefly the operation of negative edge-triggered JK flip flop with its truth table. Convert T flip-flop into JK flip-flop. ## Short answer A negative edge-triggered JK flip-flop changes state only at the falling clock edge. Truth table: J=0,K=0 holds; J=0,K=1 resets; J=1,K=0 sets; J=1,K=1 toggles. To convert a T flip-flop into a JK flip-flop, derive T = J Q_n' + K Q_n using excitation tables and K-map, then feed this expression to the T input. ## Answer #### Negative edge-triggered JK flip-flop A negative edge-triggered JK flip-flop changes state only at the **falling (HIGH-to-LOW) edge** of the clock. An edge detector produces a narrow pulse at the falling edge, and only during that pulse are J and K allowed to act. Its symbol has a triangle with a bubble at CLK. Since the inputs act for a very short time, the output can change only once per clock, so there is **no race-around**. | CLK | J | K | $Q_{n+1}$ | Action | |---|---|---|---|---| | Falling edge | 0 | 0 | $Q_n$ | No change | | Falling edge | 0 | 1 | 0 | Reset | | Falling edge | 1 | 0 | 1 | Set | | Falling edge | 1 | 1 | $Q_n'$ | Toggle | | 0, 1, rising | X | X | $Q_n$ | No change | #### Converting T flip-flop into JK flip-flop We need a circuit with inputs J, K, $Q_n$ whose output drives T. T excitation: $T = 1$ when the state must change. | J | K | $Q_n$ | $Q_{n+1}$ | T | |---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 0 | 1 | **K-map for T** ```text KQn=00 01 11 10 J=0 0 0 1 0 J=1 1 0 1 1 ``` - Cells 011, 111 ($K=1$, $Q_n=1$) give $KQ_n$. - Cells 100, 110 ($J=1$, $Q_n=0$) give $JQ_n'$. $$ T = J\,Q_n' + K\,Q_n $$ **Circuit** ```text J --[AND]--+ Q'--[ ] +--[OR]-- T +--------+--- Q K --[AND]--+ | T FF | Q --[ ] | CLK |--- Q' +--------+ (Q and Q' fed back to the AND gates) ``` Check: $J = K = 1$ gives $T = Q_n' + Q_n = 1$, so it toggles; $J = K = 0$ gives $T = 0$, no change. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. When does a negative edge-triggered JK flip-flop change state? A. At the rising edge of the clock B. While the clock is HIGH C. While the clock is LOW D. At the falling (HIGH-to-LOW) edge Answer: D. It acts only at the 1-to-0 transition, shown by a bubble with the triangle at CLK. (Key point: Negative edge) 2. Why is there no race-around in this flip-flop? A. Inputs act only for a very short time at the edge, so Q changes once per clock B. It uses two clocks C. J and K are never both 1 D. It has no feedback Answer: A. The narrow pulse ends before the new output can re-trigger it. (Key point: No race-around) 3. What input expression drives the T flip-flop when converting it to a JK flip-flop? A. T = J Qn + K Qn' B. T = J Qn' + K Qn C. T = J + K D. T = J K Answer: B. T must be 1 when the state must change: Qn=0 and J=1, or Qn=1 and K=1. (Key point: T expression) 4. With J = K = 1 in the converted circuit, what is T and the behaviour? A. T = Qn, hold B. T = 1, reset C. T = 1, toggle D. T = 0, hold Answer: C. T = Qn' + Qn = 1, so it toggles; J=K=0 gives T=0 and no change. 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