--- title: "JK over SR advantages; D flip-flop" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:jk-over-sr-d-flipflop" source: https://www.bctengineer.com/q/semester_3/digital_logic/jk-over-sr-d-flipflop site: BCT Engineering --- # JK over SR advantages; D flip-flop Digital Logic · Chapter 6: Flip Flops - Asked in: 2081 Baisakh, 2+5 marks - Video: [Lec -37: Introduction to D Flip Flop | Circuit, Working, Characteristics & Excitation Table](https://www.youtube.com/watch?v=SCZaFD9Zv1s) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/jk-over-sr-d-flipflop - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Write down the advantages of JK flip-flop over SR flip-flop. Explain the operation of D flip-flop with necessary diagrams, truth tables and timing diagram. ## Short answer JK flip-flop eliminates the invalid S=R=1 state, using J=K=1 to toggle, making it useful for counters and universal for other types. A D flip-flop copies input D to Q at each active clock edge and holds it; built by feeding D to S and D' to R, ensuring complementary inputs. ## Answer #### Advantages of J-K over S-R flip-flop - **No invalid state:** for S = R = 1 the S-R output is undefined, but J = K = 1 makes the J-K flip-flop **toggle**, a useful defined state. - Because it can toggle, it can work as a **T flip-flop** and is the basic element of counters and frequency dividers. - It is a universal flip-flop: S-R, D and T operations can all be obtained from it. - Its excitation table has many don't-cares, which gives simpler logic in counter design. #### D flip-flop A **D flip-flop** has one data input. At each active clock edge, the output Q becomes equal to D and stays so until the next active edge: $Q_{n+1} = D$. It is made from an S-R flip-flop with an inverter between S and R, so S = R = 1 never occurs. **Logic diagram** ```text D --+------------>+------+ S* +------+ | | NAND |----->| NAND |---> Q | CLK --+-->| G1 | Q'->| G3 | | | +------+ +------+ | | +------+ R* +------+ | +-->| NAND |----->| NAND |---> Q' +--[NOT]----->| G2 | Q-->| G4 | +------+ +------+ S = D and R = D' : the forbidden S=R=1 never occurs ``` **Symbol** ```text +---------+ D ---| D Q |--- Q CLK -|> | | Q' |--- Q' +---------+ ``` **Operation** - **CLK inactive:** G1 = G2 = 1, the latch keeps its previous state. - **D = 1 at the clock:** S = 1, R = 0, G1 output goes 0 and sets the latch, Q = 1. - **D = 0 at the clock:** S = 0, R = 1, G2 output goes 0 and resets the latch, Q = 0. **Truth table** | CLK | D | Q+ | Action | |---|---|---|---| | no edge | x | Q | No change | | edge | 0 | 0 | Reset | | edge | 1 | 1 | Set | **Timing diagram** (positive edge triggered, Q initially 0) ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| D ‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾‾| Q _|‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾ ``` Q copies D at each rising edge only, so the output is the input delayed by one clock period. D flip-flops are used in registers, latches for data and as delay elements. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the main advantage of J-K over S-R flip-flop? A. It needs no clock B. J = K = 1 gives a defined toggle instead of an invalid state C. It has more outputs D. It never changes state Answer: B. S = R = 1 is undefined in S-R, but J = K = 1 toggles in J-K. (Key point: No invalid state) 2. Why is the J-K flip-flop called universal? A. It works without power B. It can be used as S-R, D and T flip-flops C. It is the fastest flip-flop D. It has no feedback Answer: B. S-R, D and T operations can all be obtained from it. (Key point: Universal use) 3. What does a D flip-flop do at the active clock edge? A. Q becomes equal to D and stays so until the next active edge B. Q toggles when D = 1 C. Q is set only if D = 0 D. Q follows D continuously, even between edges Answer: A. Q(n+1) = D at the active edge only. (Key point: D flip-flop behaviour) 4. How does the D flip-flop avoid the invalid S = R = 1 state? A. The clock is disabled B. An inverter makes R = S', so S and R are complements C. The Q output is grounded D. S and R are both tied to 0 Answer: B. S = D and R = D' so they are never both 1. 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