--- title: "JK to SR flip-flop conversion" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:jk-to-sr-conversion" source: https://www.bctengineer.com/q/semester_3/digital_logic/jk-to-sr-conversion site: BCT Engineering --- # JK to SR flip-flop conversion Digital Logic · Chapter 6: Flip Flops - Asked in: 2075 Chaitra, 6 marks - Video: [Lec - 51: Convert JK to SR Flip Flop | Digital Electronics](https://www.youtube.com/watch?v=k-jzR07dY1s) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/jk-to-sr-conversion - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Convert J-K flip flop to S-R flip flop. ## Short answer To convert a J-K flip-flop to S-R, connect S directly to J and R to K. J = S, K = R, because JK=10 sets, JK=01 resets, JK=00 holds, exactly matching S-R behavior. ## Answer To make a J-K flip-flop work as an S-R flip-flop, we find J and K as functions of S, R and the present state Q. The S-R behaviour: SR = 00 hold, 01 reset, 10 set, 11 not allowed (don't care). **Step 1: excitation table of the J-K flip-flop** | Q | Q+ | J | K | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | x | | 1 | 0 | x | 1 | | 1 | 1 | x | 0 | **Step 2: conversion table** | S | R | Q | Q+ | J | K | |---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | x | | 0 | 0 | 1 | 1 | x | 0 | | 0 | 1 | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | x | 1 | | 1 | 0 | 0 | 1 | 1 | x | | 1 | 0 | 1 | 1 | x | 0 | | 1 | 1 | 0 | x | x | x | | 1 | 1 | 1 | x | x | x | **Step 3: K-maps** ```text K-map for J Q\SR 00 01 11 10 0 0 0 x 1 1 x x x x K-map for K Q\SR 00 01 11 10 0 x x x x 1 0 1 x 0 ``` - For J: the only 1 is at Q = 0, SR = 10. Grouping it with the don't-cares in column SR = 11 and in row Q = 1 gives $J = S$. - For K: the only 1 is at Q = 1, SR = 01. Grouping with the don't-cares gives $K = R$. $$ J = S, \qquad K = R $$ **Step 4: circuit** ```text +---------+ S -------| J Q |--- Q CLK -----|> JK | R -------| K Q' |--- Q' +---------+ ``` So S is connected straight to J and R straight to K. Check: SR = 10 gives JK = 10 (set), SR = 01 gives JK = 01 (reset), SR = 00 gives JK = 00 (hold), which is the S-R table. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why are the S = R = 1 rows don't-cares in the conversion table? A. Because S-R does not allow that input B. Because the J-K always toggles C. Because Q is unknown D. Because the clock is off Answer: A. S = R = 1 is forbidden for an S-R flip-flop, so those outputs are don't-cares. (Key point: Don't-care rows) 2. What is J in terms of S and R? A. J = R B. J = S C. J = S' D. J = S R Answer: B. The K-map for J gives J = S. (Key point: J expression) 3. What is K in terms of S and R? A. K = R B. K = S C. K = R' D. K = Q Answer: A. The K-map for K gives K = R. (Key point: K expression) 4. If SR = 01, what do the J and K inputs do? A. Set the flip-flop (JK = 10) B. Hold the flip-flop C. Reset the flip-flop (JK = 01) D. Toggle the flip-flop Answer: C. Since J = S and K = R, SR = 01 gives JK = 01, which resets. (Key point: Check) ## Related in Digital Logic - [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [Flip-flop as state machine; SR to JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aflipflop-state-machine-sr-to-jk) — Digital Logic, chapter 6 - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× - [JK over SR advantages; D flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-over-sr-d-flipflop) — Digital Logic, chapter 6 - [T to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3At-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [Negative edge JK flip-flop; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-negative-edge-t-to-jk) — Digital Logic, chapter 6 ## Related in other subjects - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6× - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9