---
title: "K-map Σ(0,2,3,4,7,8,10,13)+d, logic circuit"
subject: "Digital Logic"
chapter: 3
key: "semester_3/digital_logic:kmap-logic-circuit-0234"
source: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-logic-circuit-0234
site: BCT Engineering
---

# K-map Σ(0,2,3,4,7,8,10,13)+d, logic circuit

Digital Logic · Chapter 3: Combinational Logic Circuits

- Asked in: 2075 Chaitra, 4+2 marks
- Video: [Don't Care (X) Conditions in K-Map - Karnaugh Map ( Solved Examples ) - Design using NAND Gate only](https://www.youtube.com/watch?v=5OX-4g6kqTw) — CS Engineering Gyan
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-logic-circuit-0234
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3

## Question

Simplify the following expressions using K-map and also draw the logical circuit. Y(A,B,C,D) = Σ(0,2,3,4,7,8,10,13) and d = Σ(5,6,12)

## Short answer

Simplified Y = A' C + B' D' + B C'. Logic circuit: three 2-input AND gates for terms A'C, B'D', BC' and one 3-input OR gate; inverters generate A', B', C', D'. (Alternatively, the B'D' AND can be replaced by a NOR if desired.)

## Answer

Given $Y(A,B,C,D) = \Sigma m(0,2,3,4,7,8,10,13) + d(5,6,12)$.

#### K-map simplification

```text
        CD
AB      00  01  11  10
      +---+---+---+---+
 00   | 1 | 0 | 1 | 1 |
      +---+---+---+---+
 01   | 1 | X | 1 | X |
      +---+---+---+---+
 11   | X | 1 | 0 | 0 |
      +---+---+---+---+
 10   | 1 | 0 | 0 | 1 |
      +---+---+---+---+
```

- Quad m(2,3,6,7) → $\overline{A}C$
- Quad m(0,2,8,10) → $\overline{B}\,\overline{D}$
- Quad m(4,5,12,13) → $B\overline{C}$

$$
Y = \overline{A}C + \overline{B}\,\overline{D} + B\overline{C}
$$

Check: 2, 3, 7 by $\overline{A}C$ (with 6); 0, 2, 8, 10 by $\overline{B}\,\overline{D}$; 4, 13 by $B\overline{C}$ (with 5, 12). All 8 minterms are covered with three quads.

#### Logic circuit

```text
A ─[NOT]─ A' ─┐
C ────────────┴─[AND]── A'C ──┐
B ─[NOT]─ B' ─┐               │
D ─[NOT]─ D' ─┴─[AND]── B'D' ─┼─[OR]── Y
B ────────────┐               │
C ─[NOT]─ C' ─┴─[AND]── BC' ──┘
```

Gates: 4 NOT gates, three 2-input AND gates and one 3-input OR gate. (As $\overline{B}\,\overline{D} = \overline{B+D}$, that AND with two inverters can be replaced by one NOR gate.)

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which term comes from the quad m(4,5,12,13) (using don't-cares 5 and 12)?
   A. B'C
   B. BC'
   C. A'B
   D. CD'
   Answer: B. In cells 4, 5, 12, 13, B = 1 and C = 0 are constant, giving BC'. (Key point: Quad with don't-cares)

2. What is the simplified expression for Y = Σ(0,2,3,4,7,8,10,13) + d(5,6,12)?
   A. A'C + B'D' + BC'
   B. A'C + BD + B'C'
   C. AC' + B'D' + BC
   D. A'C + B'D + BC'
   Answer: A. Quads give A'C (2,3,6,7), B'D' (0,2,8,10) and BC' (4,5,12,13). (Key point: Simplified Y)

3. How many gates does the AND-OR realization need?
   A. 3 NOT, 3 AND, 1 OR
   B. 4 NOT, 3 AND, 1 three-input OR
   C. 2 NOT, 2 AND, 1 OR
   D. 4 NOT, 4 AND, 2 OR
   Answer: B. Complements A', B', C', D' need 4 NOTs, there are three 2-input ANDs and one 3-input OR. (Key point: Circuit gate count)

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