--- title: "K-map Π(0,1,4,7,8,10,11,12)+d, NAND" subject: "Digital Logic" chapter: 3 key: "semester_3/digital_logic:kmap-maxterm-nand-0147" source: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-maxterm-nand-0147 site: BCT Engineering --- # K-map Π(0,1,4,7,8,10,11,12)+d, NAND Digital Logic · Chapter 3: Combinational Logic Circuits - Asked in: 2078 Kartik, 4+2 marks - Video: [Make a K-map for the function, f(A,B,C,D) = ΠM (3,4,5,7,11,13,15) + d(6,8,10,12)](https://www.youtube.com/watch?v=_7GvhFRMggs) — Room No. 547 - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-maxterm-nand-0147 - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3 ## Question Simplify the given function using K-map F = Π(0,1,4,7,8,10,11,12) and D = (2,3,6,9,15) and implement the final expression using NAND gate only. ## Short answer Simplified expression: F = B C' D + B C D' = B(C⊕D). NAND-only implementation: convert to NAND-NAND form F = ((B C' D)' · (B C D')')' using NAND gates for inverters (tied inputs) and product terms. Requires 5 NAND gates. ## Answer Given $F = \Pi M(0,1,4,7,8,10,11,12)$ with don't-cares $d(2,3,6,9,15)$. The maxterms are the 0-cells, so the 1-cells are 5, 13, 14. #### K-map ```text CD AB 00 01 11 10 +---+---+---+---+ 00 | 0 | 0 | X | X | +---+---+---+---+ 01 | 0 | 1 | 0 | X | +---+---+---+---+ 11 | 0 | 1 | X | 1 | +---+---+---+---+ 10 | 0 | X | 0 | 0 | +---+---+---+---+ ``` Grouping the 1s (don't-care 6 is used with 14): - Pair m(5,13) → $B\overline{C}D$ - Pair m(6,14) → $BC\overline{D}$ $$ F = B\overline{C}D + BC\overline{D} = B(C \oplus D) $$ Check: 5 and 13 by $B\overline{C}D$; 14 by $BC\overline{D}$. ($ABC$, cells 14 and 15, can replace the second term with the same cost.) #### NAND-only implementation An SOP expression maps directly to a two-level NAND-NAND circuit (De Morgan: $X + Y = \overline{\overline{X}\cdot\overline{Y}}$). Each product term becomes a first-level NAND and the output NAND replaces the OR gate. Complemented inputs are made with NAND gates whose inputs are tied. $$ F = \overline{\overline{B\overline{C}D}\cdot\overline{BC\overline{D}}} $$ ```text C ──[NAND]── C' (inputs tied) D ──[NAND]── D' (inputs tied) B, C', D ──[NAND]── P1 ─┐ ├──[NAND]── F B, C, D' ──[NAND]── P2 ─┘ ``` Gates: 2 NAND inverters, two 3-input NANDs and one 2-input output NAND: 5 NAND gates. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. For F = ΠM(0,1,4,7,8,10,11,12) with don't-cares d(2,3,6,9,15), which cells are the required 1-cells? A. 0, 1, 4, 8, 12 B. 2, 3, 6, 9, 15 C. 5, 13, 14 D. 5, 6, 13, 14 Answer: C. The maxterms are 0-cells and the d-cells are optional, so the remaining cells 5, 13 and 14 are the 1s. (Key point: 1-cells from a maxterm list) 2. Which pair of cells gives the term B C D' in the simplified function? A. m(5,13) B. m(6,14), using don't-care 6 C. m(12,14) D. m(4,12) Answer: B. Don't-care 6 is grouped with required 1-cell 14, giving BCD'. (Key point: Using a don't-care in grouping) 3. What is the simplified result? A. F = B'CD + BC'D' B. F = B(C + D) C. F = B(C ⊕ D) D. F = B(C ⊙ D) Answer: C. F = BC'D + BCD' = B(C ⊕ D). (Key point: Simplified expression) 4. How is the SOP F = BC'D + BCD' built using NAND gates only? A. Each product term goes to an AND gate, then one NAND for the sum B. Each product term is a first-level NAND, and an output NAND replaces the OR gate C. All terms are fed to a single NOR gate D. Each term uses a NOT gate followed by an OR gate Answer: B. By De Morgan, X + Y = (X'·Y')', so NAND-NAND gives SOP directly; complemented inputs use NANDs with tied inputs. (Key point: NAND-NAND realization) ## Related in Digital Logic - [K-map Σ(0,1,4,8,10,11,12)+d, NAND-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-only-01248) — Digital Logic, chapter 3 - [K-map Σm(0,1,2,4,7,8,9,10,12,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-only-01247) — Digital Logic, chapter 3 - [K-map Σ(1,2,3,8,9,10,11,14)+d(0,4,12), NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-1238-dc-0412) — Digital Logic, chapter 3, asked 5× - [K-map ΠM(0,2,3,8,10,11,12,15)+d, NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-maxterm-nor-0238) — Digital Logic, chapter 3 - [Minterms/maxterms; K-map Σm(0,1,2,4,5,9,12,15)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-nand-0124) — Digital Logic, chapter 3 - [K-map Σ(1,3,7,11,15)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-1371115) — Digital Logic, chapter 3, asked 5× ## Related in other subjects - [K-map with don't cares, NAND only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-dont-care-nand) — Basic Electronics Engineering, chapter 6 - [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6 - [Asphalt Institute design: 5.11×10⁴ ESAL/year, 12 years](https://www.bctengineer.com/question.md?key=semester_7%2Ftransportation_engineering_ii%3Aasphalt-institute-design-5-11e4-esal) — Transportation Engineering II, chapter 2 - [K-map and universal gate: xy + x'z + yz](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-universal-gate-xy) — Basic Electronics Engineering, chapter 6