---
title: "K-map ΠM(0,2,3,8,10,11,12,15)+d, NOR"
subject: "Digital Logic"
chapter: 3
key: "semester_3/digital_logic:kmap-maxterm-nor-0238"
source: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-maxterm-nor-0238
site: BCT Engineering
---

# K-map ΠM(0,2,3,8,10,11,12,15)+d, NOR

Digital Logic · Chapter 3: Combinational Logic Circuits

- Asked in: 2076 Asoj, 5+2 marks
- Video: [Minimize the following expression using K map and realize using NOR gate](https://www.youtube.com/watch?v=2HpvaRRDPK8) — Maharshi Sanand Yadav T
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-maxterm-nor-0238
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3

## Question

Simplify the following function using K-map. And also draw reduced circuit using NOR gate y(A,B,C,D) = ΠM(0,2,3,8,10,11,12,15) and d = ΠM(7,13,14).

## Short answer

The simplified SOP is y = A'B + C'D. Implement with NOR gates: use NOR inverters to get B' and D', then NOR gates for (A+B')' and (C+D')', combine with a NOR to get y', and a final NOR inverter to produce y.

## Answer

Given $y(A,B,C,D) = \Pi M(0,2,3,8,10,11,12,15)$ with don't-cares $d = 7, 13, 14$. The listed maxterms are the 0-cells; the remaining cells 1, 4, 5, 6, 9 are 1s.

#### K-map

```text
        CD
AB      00  01  11  10
      +---+---+---+---+
 00   | 0 | 1 | 0 | 0 |
      +---+---+---+---+
 01   | 1 | 1 | X | 1 |
      +---+---+---+---+
 11   | 0 | X | 0 | X |
      +---+---+---+---+
 10   | 0 | 1 | 0 | 0 |
      +---+---+---+---+
```

#### Simplified POS (grouping the 0s)

- Quad of 0s M(12,13,14,15) → $(\overline{A}+\overline{B})$
- Quad of 0s M(0,2,8,10) → $(B+D)$
- Quad of 0s M(3,7,11,15) → $(\overline{C}+\overline{D})$

$$
y = (\overline{A}+\overline{B})(B+D)(\overline{C}+\overline{D})
$$

#### Simplified SOP (grouping the 1s)

- Quad m(4,5,6,7) → $\overline{A}B$
- Quad m(1,5,9,13) → $\overline{C}D$

$$
y = \overline{A}B + \overline{C}D
$$

Both forms are correct. The SOP form has only 2 terms and 4 literals, so it gives the smaller NOR circuit.

#### Reduced circuit using NOR gates

Each product term becomes a NOR of complemented literals:
$$
\begin{aligned} \overline{A}B &= \overline{A+\overline{B}} \\ \overline{C}D &= \overline{C+\overline{D}} \\ y &= \overline{\overline{\overline{A}B+\overline{C}D}} \end{aligned}
$$

```text
B ──[NOR]── B'   (inputs tied)
D ──[NOR]── D'   (inputs tied)

A, B' ──[NOR]── P1  ─┐
                     ├──[NOR]── y'
C, D' ──[NOR]── P2  ─┘

y' ──[NOR]── y   (inputs tied)
```

Gates: 2 NOR inverters, 2 first-level NORs, 1 NOR giving $\overline{y}$ and 1 NOR inverter: 6 two-input NOR gates.

(The POS form could be built as a NOR-NOR circuit, $y = \overline{\overline{\overline{A}+\overline{B}} + \overline{B+D} + \overline{\overline{C}+\overline{D}}}$, but it needs 8 NOR gates including inverters.)

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. 1s are cells:
   A. 1,4,5,6,9
   B. 0,2,3
   C. 7,13,14
   D. 8,10,11
   Answer: A. Remaining cells. (Key point: Ones)

2. SOP:
   A. AB + CD
   B. A'B + C'D
   C. A'B' + CD
   D. BD
   Answer: B. Quads. (Key point: SOP)

3. Why SOP used?
   A. POS impossible
   B. POS wrong
   C. 2 terms, 4 literals, smaller NOR circuit
   D. SOP required
   Answer: C. POS needs 8 NORs. (Key point: Choice)

4. SOP NOR gates:
   A. 8
   B. 4
   C. 5
   D. 6
   Answer: D. 2 inv, 2, 1, 1. (Key point: Gates)

## Related in Digital Logic

- [K-map Σm(7,9,12,13,14,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-sum-7-9-12) — Digital Logic, chapter 3
- [K-map Σ(0,1,4,8,10,11,12)+d, NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-gates-01248) — Digital Logic, chapter 3, asked 5×
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- [K-map Σ(1,2,3,8,9,10,11,14)+d(0,4,12), NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-1238-dc-0412) — Digital Logic, chapter 3, asked 5×