--- title: "K-map Σ(1,2,3,8,9,10,11,14)+d(0,4,12), NAND" subject: "Digital Logic" chapter: 3 key: "semester_3/digital_logic:kmap-nand-1238-dc-0412" source: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-nand-1238-dc-0412 site: BCT Engineering --- # K-map Σ(1,2,3,8,9,10,11,14)+d(0,4,12), NAND Digital Logic · Chapter 3: Combinational Logic Circuits - Asked in: 2079 Bhadra, 4+2 marks; 2079 Baisakh, 3+3 marks; 2076 Chaitra, 4+2 marks (asked 3 times) - Video: [Don't Care (X) Conditions in K-Map - Karnaugh Map ( Solved Examples ) - Design using NAND Gate only](https://www.youtube.com/watch?v=5OX-4g6kqTw) — CS Engineering Gyan - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-nand-1238-dc-0412 - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3 ## Question Simplify the function using K-map F = Σ(1,2,3,8,9,10,11,14) and D = Σ(0,4,12). Also realize the simplified circuit using NAND Gates. ## Short answer K-map simplification yields F = B' + A D'. For NAND realization, apply double inversion and DeMorgan: F = NAND(B, NAND(A, D')). Use a NAND gate with tied inputs as an inverter for D; total three NAND gates. ## Answer Given $F(A,B,C,D) = \Sigma m(1,2,3,8,9,10,11,14) + d(0,4,12)$, where X marks a don't-care cell. #### K-map simplification ```text CD AB 00 01 11 10 +---+---+---+---+ 00 | X | 1 | 1 | 1 | +---+---+---+---+ 01 | X | 0 | 0 | 0 | +---+---+---+---+ 11 | X | 0 | 0 | 1 | +---+---+---+---+ 10 | 1 | 1 | 1 | 1 | +---+---+---+---+ ``` Groups (don't-cares 0 and 12 are used where they make a group bigger; don't-care 4 is left out): - Octet m(0,1,2,3,8,9,10,11) → $\overline{B}$ - Quad m(8,10,12,14) → $A\overline{D}$ $$ F = \overline{B} + A\overline{D} $$ Check: the octet covers 1, 2, 3, 8, 9, 10, 11, and the quad covers 8, 10, 14 (with 12). All minterms are covered. #### Realization using NAND gates Take double complement and apply De Morgan's theorem: $$ \begin{aligned} F &= \overline{\overline{\overline{B} + A\overline{D}}} \\ &= \overline{B \cdot \overline{A\overline{D}}} \end{aligned} $$ So $F$ = NAND($B$, NAND($A$, $\overline{D}$)). $\overline{D}$ is made with a NAND gate whose inputs are tied together. The single literal $\overline{B}$ goes into the output NAND as plain $B$. ```text D ──[NAND]── D' (inputs tied) A, D' ──[NAND]── P1 ─┐ ├──[NAND]── F B ────────── ─┘ ``` Total: 3 two-input NAND gates (one used as an inverter). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Simplified F: A. B' + AD' B. B + AD' C. B' + A'D D. B'D' Answer: A. Octet gives B', quad (8,10,12,14) gives AD'. (Key point: Simplified F) 2. Don't care 4 is: A. Used in the octet B. Not used in any group C. Used in the quad D. Treated as 0 Answer: B. Cells 0 and 12 enlarge groups; 4 is left out. (Key point: Don't cares) 3. F in NAND form: A. (B' . AD')' B. B NAND A C. (B . (A D')')' D. (B+AD')' Answer: C. Double complement and De Morgan. (Key point: NAND form) 4. NAND gates used: A. 2 B. 4 C. 5 D. 3 Answer: D. One inverter, one NAND for A D', and the output NAND. (Key point: Gate count) ## Close variants set in other exams - [K-map Σ(1,3,7,11,15)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-1371115) — Digital Logic, chapter 3, asked 5× - [K-map Σ(0,1,4,8,10,11,12)+d, NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-gates-01248) — Digital Logic, chapter 3, asked 5× ## Related in Digital Logic - [K-map Σ(0,1,4,8,10,11,12)+d, realize circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-realize-circuit-01248) — Digital Logic, chapter 3, asked 2× - [K-map Σ(0,1,4,8,10,11,12)+d, NAND-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-only-01248) — Digital Logic, chapter 3 - [K-map Π(0,1,4,7,8,10,11,12)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-maxterm-nand-0147) — Digital Logic, chapter 3 - [Minterms/maxterms; K-map Σ(1,3,5,8,10,11,12)+d](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-1358) — Digital Logic, chapter 3, asked 2× - [K-map ΠM(0,2,3,8,10,11,12,15)+d, NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-maxterm-nor-0238) — Digital Logic, chapter 3 - [K-map Σ(1,2,3,8,9,10,11,13,14)+d, POS](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-pos-form-12389) — Digital Logic, chapter 3 ## Related in other subjects - [K-map with don't cares, NAND only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-dont-care-nand) — Basic Electronics Engineering, chapter 6 - [K-map: x'yz + x'y'z + xyz with gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-xyz-realize-gates) — Basic Electronics Engineering, chapter 6, asked 2× - [Class C pool for 10, 12, 8, 14](https://www.bctengineer.com/question.md?key=semester_7%2Fcomputer_networks_and_security%3Asubnetting-class-c-four-depts) — Computer Networks and Security, chapter 4, asked 2×