--- title: "K-map Σ(1,3,7,11,15)+d, NAND" subject: "Digital Logic" chapter: 3 key: "semester_3/digital_logic:kmap-nand-1371115" source: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-nand-1371115 site: BCT Engineering --- # K-map Σ(1,3,7,11,15)+d, NAND Digital Logic · Chapter 3: Combinational Logic Circuits - Asked in: 2080 Bhadra, 4+2 marks - Video: [Don't Care (X) Conditions in K-Map - Karnaugh Map ( Solved Examples ) - Design using NAND Gate only](https://www.youtube.com/watch?v=5OX-4g6kqTw) — CS Engineering Gyan - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-nand-1371115 - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3 ## Question Simplify the function using K-map F = Σ(1,3,7,11,15) and D = Σ(0,2,5,8,14). Also realize the simplified circuit using NAND Gates. ## Short answer K-map simplification gives F = CD + A'D = D(C + A'). Realized with NAND gates: one inverter for A', two 2-input NANDs for CD and A'D, and one output NAND. ## Answer Given $F(A,B,C,D) = \Sigma m(1,3,7,11,15) + d(0,2,5,8,14)$. #### K-map simplification ```text CD AB 00 01 11 10 +---+---+---+---+ 00 | X | 1 | 1 | X | +---+---+---+---+ 01 | 0 | X | 1 | 0 | +---+---+---+---+ 11 | 0 | 0 | 1 | X | +---+---+---+---+ 10 | X | 0 | 1 | 0 | +---+---+---+---+ ``` - Quad m(3,7,11,15) → $CD$ - Quad m(1,3,5,7) → $\overline{A}D$ $$ F = CD + \overline{A}D = D(C + \overline{A}) $$ Check: 3, 7, 11, 15 by $CD$; 1 (with 3, 5, 7) by $\overline{A}D$. Don't-care 5 helps form the $\overline{A}D$ quad. ($\overline{A}\,\overline{B}$ in place of $\overline{A}D$ is an equally small alternative.) #### Realization using NAND gates $$ \begin{aligned} F &= \overline{\overline{CD + \overline{A}D}} \\ &= \overline{\overline{CD}\cdot\overline{\overline{A}D}} \end{aligned} $$ ```text A ──[NAND]── A' (inputs tied) C, D ──[NAND]── P1 ─┐ ├──[NAND]── F A', D ──[NAND]── P2 ─┘ ``` Gates: one NAND inverter for $\overline{A}$, two 2-input NANDs and one 2-input output NAND: 4 NAND gates. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which minterms form the quad that gives CD? A. 3,7,11,15 B. 1,3,5,7 C. 8,9,12,13 D. 0,2,8,10 Answer: A. Cells 3,7,11,15 have C=1 and D=1. (Key point: Quad CD) 2. Why is don't-care 5 helpful? A. It completes the quad 1,3,5,7 giving A'D B. It makes the function zero C. It must always be 0 D. It is part of CD Answer: A. Setting 5 to 1 lets minterm 1 join the quad m(1,3,5,7) = A'D. (Key point: Using don't-care 5) 3. What is the simplified F? A. CD + A'D B. CD + AD C. C + D D. A'C + D' Answer: A. F = CD + A'D = D(C + A'). (Key point: Simplified function) 4. How many NAND gates are needed to realize F = CD + A'D? A. 3 B. 4 C. 5 D. 6 Answer: B. One inverter for A', two first-level NANDs and one output NAND: 4 gates. (Key point: NAND realization) ## Close variants set in other exams - [K-map Σ(1,2,3,8,9,10,11,14)+d(0,4,12), NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-1238-dc-0412) — Digital Logic, chapter 3, asked 5× - [K-map Σ(0,1,4,8,10,11,12)+d, NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-gates-01248) — Digital Logic, chapter 3, asked 5× ## Related in Digital Logic - [K-map Σ(0,1,4,8,10,11,12)+d, realize circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-realize-circuit-01248) — Digital Logic, chapter 3, asked 2× - [K-map Σm(7,9,12,13,14,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-sum-7-9-12) — Digital Logic, chapter 3 - [K-map Σ(0,1,4,8,10,11,12)+d, NAND-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-only-01248) — Digital Logic, chapter 3 - [K-map Σm(0,1,2,8,10,14,15)+d, POS with NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-pos-nor-0128) — Digital Logic, chapter 3 - [K-map Π(0,1,4,7,8,10,11,12)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-maxterm-nand-0147) — Digital Logic, chapter 3 - [Minterms/maxterms; K-map Σm(2,4,5,13,14)+d, universal gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-universal) — Digital Logic, chapter 3 ## Related in other subjects - [K-map with don't cares, NAND only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-dont-care-nand) — Basic Electronics Engineering, chapter 6 - [K-map: x'yz + x'y'z + xyz with gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-xyz-realize-gates) — Basic Electronics Engineering, chapter 6, asked 2× - [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6 - [Why NOR and NAND are universal gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Auniversal-gates-nor-nand) — Basic Electronics Engineering, chapter 6