---
title: "K-map Σ(0,1,4,8,10,11,12)+d, NAND-only"
subject: "Digital Logic"
chapter: 3
key: "semester_3/digital_logic:kmap-nand-only-01248"
source: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-nand-only-01248
site: BCT Engineering
---

# K-map Σ(0,1,4,8,10,11,12)+d, NAND-only

Digital Logic · Chapter 3: Combinational Logic Circuits

- Asked in: 2075 Chaitra, 6 marks
- Video: [Minimise The Equation Using K-map And Realize It Using NAND Gates Only Y=Σm(0,1,2,3,5,7,8,9,11,14)](https://www.youtube.com/watch?v=XGGRFADgyFA) — Bhuvaneshwari N EE & EC
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-nand-only-01248
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3

## Question

Simplify the function using K-map F = Σ(0,1,4,8,10,11,12) and D = Σ(2,3,6,9,15). Also convert the result into only NAND gates.

## Short answer

The simplified expression is F = B' + C'D'. Using NAND gates: generate C' and D' with NAND inverters, compute (C' NAND D') as P1, then F = B NAND P1, requiring four 2-input NAND gates.

## Answer

Given $F(A,B,C,D) = \Sigma m(0,1,4,8,10,11,12) + d(2,3,6,9,15)$.

#### K-map simplification

```text
        CD
AB      00  01  11  10
      +---+---+---+---+
 00   | 1 | 1 | X | X |
      +---+---+---+---+
 01   | 1 | 0 | 0 | X |
      +---+---+---+---+
 11   | 1 | 0 | X | 0 |
      +---+---+---+---+
 10   | 1 | X | 1 | 1 |
      +---+---+---+---+
```

Groups (don't-cares 2, 3, 9 complete the octet; 6 and 15 are not used):

- Octet m(0,1,2,3,8,9,10,11) → $\overline{B}$
- Quad m(0,4,8,12) → $\overline{C}\,\overline{D}$

$$
F = \overline{B} + \overline{C}\,\overline{D}
$$

Check: the octet covers 0, 1, 8, 10, 11 and the quad covers 0, 4, 8, 12.

#### Conversion to NAND gates only

$$
\begin{aligned} F &= \overline{\overline{\overline{B}+\overline{C}\,\overline{D}}} \\ &= \overline{B\cdot\overline{\overline{C}\,\overline{D}}} \end{aligned}
$$

So $F$ = NAND($B$, NAND($\overline{C}$, $\overline{D}$)). The complements $\overline{C}$ and $\overline{D}$ come from NAND gates with tied inputs. The single literal $\overline{B}$ enters the output NAND as plain $B$.

```text
C ──[NAND]── C'   (inputs tied)
D ──[NAND]── D'   (inputs tied)

C', D' ──[NAND]── P1  ─┐
                       ├──[NAND]── F
B      ──────────     ─┘
```

Total: 4 two-input NAND gates (two as inverters).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. F:
   A. B + CD
   B. B'C'
   C. B'+D
   D. B' + C'D'
   Answer: D. Octet and quad. (Key point: Simplified)

2. Octet needs don't cares:
   A. 2,3,9
   B. 6,15
   C. 4
   D. 12
   Answer: A. m(0..3,8..11). (Key point: Octet)

3. NAND form:
   A. (B' . CD)'
   B. (B . (C'D')')'
   C. B NAND C
   D. (B+C')'
   Answer: B. Double complement. (Key point: NAND)

4. NAND gates:
   A. 3
   B. 5
   C. 4
   D. 2
   Answer: C. Two inverters, 2. (Key point: Gates)

## Related in Digital Logic

- [K-map Π(0,1,4,7,8,10,11,12)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-maxterm-nand-0147) — Digital Logic, chapter 3
- [K-map Σ(1,2,3,8,9,10,11,14)+d(0,4,12), NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-1238-dc-0412) — Digital Logic, chapter 3, asked 5×
- [K-map Σm(0,1,2,4,7,8,9,10,12,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-only-01247) — Digital Logic, chapter 3
- [Minterms/maxterms; K-map Σm(0,1,2,4,5,9,12,15)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-nand-0124) — Digital Logic, chapter 3
- [K-map ΠM(0,2,3,8,10,11,12,15)+d, NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-maxterm-nor-0238) — Digital Logic, chapter 3
- [K-map Σ(1,3,7,11,15)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-1371115) — Digital Logic, chapter 3, asked 5×

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