---
title: "K-map ΠM(0,2,4,6,7,8,10,13,15) and 8:1 MUX"
subject: "Digital Logic"
chapter: 3
key: "semester_3/digital_logic:kmap-pom-8to1-mux"
source: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-pom-8to1-mux
site: BCT Engineering
---

# K-map ΠM(0,2,4,6,7,8,10,13,15) and 8:1 MUX

Digital Logic · Chapter 3: Combinational Logic Circuits

- Asked in: 2081 Bhadra, 4+2 marks
- Video: [K' Map using Max Terms (Part 2)](https://www.youtube.com/watch?v=lPT9Ltjij1s) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-pom-8to1-mux
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3

## Question

Simplify the following Boolean logic function using K-map. Also realize the logic function using an 8:1 multiplexer and necessary logic gates. Y(A,B,C,D) = ΠM(0,2,4,6,7,8,10,13,15)

## Short answer

Minimal SOP: Y = B'D + A'C'D + ABD'. Using an 8:1 multiplexer with A, B, C as select lines: I0=I1=I2=I4=I5 = D, I3 = 0, I6=I7 = D'. One inverter generates D'.

## Answer

$Y(A,B,C,D) = \Pi M(0,2,4,6,7,8,10,13,15)$ means Y = 0 at these cells. So Y = 1 at the remaining cells:
$$
Y = \Sigma m(1,3,5,9,11,12,14)
$$

#### K-map simplification

```text
        CD
AB      00  01  11  10
      +---+---+---+---+
 00   | 0 | 1 | 1 | 0 |
      +---+---+---+---+
 01   | 0 | 1 | 0 | 0 |
      +---+---+---+---+
 11   | 1 | 0 | 0 | 1 |
      +---+---+---+---+
 10   | 0 | 1 | 1 | 0 |
      +---+---+---+---+
```

Grouping the 1s:

- Quad m(1,3,9,11) → $\overline{B}D$
- Pair m(1,5) → $\overline{A}\,\overline{C}D$
- Pair m(12,14) → $AB\overline{D}$

$$
Y = B'D + A'C'D + ABD'
$$

(Grouping the 0s gives the minimal POS $Y = (A+D)(B+D)(\overline{A}+\overline{B}+\overline{D})(\overline{B}+\overline{C}+\overline{D})$, which has more terms, so the SOP form is used.)

#### Realization with an 8:1 multiplexer

Use A, B, C as the select lines $S_2 S_1 S_0$ and connect each data input $I_0$–$I_7$ to 0, 1, D or $\overline{D}$. For each value of ABC, compare Y for D = 0 and D = 1:

| ABC (sel) | Minterms | Y at D=0 | Y at D=1 | Data input |
|---|---|---|---|---|
| 000 | 0, 1 | 0 | 1 | $I_0 = D$ |
| 001 | 2, 3 | 0 | 1 | $I_1 = D$ |
| 010 | 4, 5 | 0 | 1 | $I_2 = D$ |
| 011 | 6, 7 | 0 | 0 | $I_3 = 0$ |
| 100 | 8, 9 | 0 | 1 | $I_4 = D$ |
| 101 | 10, 11 | 0 | 1 | $I_5 = D$ |
| 110 | 12, 13 | 1 | 0 | $I_6 = \overline{D}$ |
| 111 | 14, 15 | 1 | 0 | $I_7 = \overline{D}$ |

```text
          +-----------+
 D  ───── | I0        |
 D  ───── | I1        |
 D  ───── | I2        |
 0  ───── | I3  8:1   |── Y
 D  ───── | I4  MUX   |
 D  ───── | I5        |
 D' ───── | I6        |
 D' ───── | I7        |
          +-----------+
           S2  S1  S0
           A   B   C

 D ──[NOT]── D'
```

Only one NOT gate is needed besides the multiplexer. Check: for $ABC = 110$, Y = $\overline{D}$, so minterm 12 (D=0) gives 1 and minterm 13 gives 0, as required.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. PiM(0,2,4,6,7,8,10,13,15) means:
   A. Y=0 at these cells, 1 elsewhere
   B. Y=1 at these cells
   C. Y=0 elsewhere
   D. Don't cares
   Answer: A. Maxterms are zeros. (Key point: Minterms)

2. Minimal SOP:
   A. BD + AC
   B. B'D + A'C'D + ABD'
   C. A'B + CD
   D. B'D' + AC
   Answer: B. From the three groups. (Key point: SOP)

3. MUX select lines:
   A. A, B, D
   B. B, C, D
   C. A, B, C with data from D
   D. All four
   Answer: C. Data inputs are 0, 1, D or D'. (Key point: Selects)

4. I6 (ABC=110) equals:
   A. D
   B. 0
   C. 1
   D. D'
   Answer: D. Y is 1 at minterm 12 (D=0), 0 at 13. (Key point: I6)

## Related in Digital Logic

- [K-map Σ(0,2,3,4,7,8,10,13)+d, logic circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-logic-circuit-0234) — Digital Logic, chapter 3
- [Function Σm(0,2,3,5,7,8,10,13,15) using 1:8 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademux-1to8-realize-function) — Digital Logic, chapter 4
- [K-map Σm(7,9,12,13,14,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-sum-7-9-12) — Digital Logic, chapter 3
- [Minterms/maxterms; K-map Σm(2,4,5,13,14)+d, universal gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-universal) — Digital Logic, chapter 3
- [K-map Σm(0,1,2,4,7,8,9,10,12,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-only-01247) — Digital Logic, chapter 3
- [32:1 MUX tree; implement Σm(0,1,3,8,9,13,15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function-15) — Digital Logic, chapter 4

## Related in other subjects

- [K-map: x'yz + x'y'z + xyz with gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-xyz-realize-gates) — Basic Electronics Engineering, chapter 6, asked 2×
- [Multiplexer and 4:1 MUX](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Amultiplexer-4-1) — Basic Electronics Engineering, chapter 6, asked 2×
- [Short note: Logic gates](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-logic-gates) — Basic Electrical and Electronics Engineering, chapter 3
