--- title: "K-map Σ(0,1,4,8,10,11,12)+d, realize circuit" subject: "Digital Logic" chapter: 3 key: "semester_3/digital_logic:kmap-realize-circuit-01248" source: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-realize-circuit-01248 site: BCT Engineering --- # K-map Σ(0,1,4,8,10,11,12)+d, realize circuit Digital Logic · Chapter 3: Combinational Logic Circuits - Asked in: 2074 Asoj, 6 marks - Video: [Don't Care (X) Conditions in K-Map - Karnaugh Map ( Solved Examples ) - Design using NAND Gate only](https://www.youtube.com/watch?v=5OX-4g6kqTw) — CS Engineering Gyan - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-realize-circuit-01248 - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3 ## Question Simplify the function using K-map F = Σ(0,1,4,8,10,11,12) and D = Σ(2,3,6,9,15). Also realize the simplified logic circuit. ## Short answer The simplified function is F = B' + C'D'. The circuit uses a NOT gate for B, a NOR gate for C and D to produce (C+D)' = C'D', and an OR gate to combine B' and the NOR output, yielding F. ## Answer Given $F(A,B,C,D) = \Sigma m(0,1,4,8,10,11,12) + d(2,3,6,9,15)$. #### K-map simplification ```text CD AB 00 01 11 10 +---+---+---+---+ 00 | 1 | 1 | X | X | +---+---+---+---+ 01 | 1 | 0 | 0 | X | +---+---+---+---+ 11 | 1 | 0 | X | 0 | +---+---+---+---+ 10 | 1 | X | 1 | 1 | +---+---+---+---+ ``` Groups (don't-cares 2, 3, 9 complete the octet; 6 and 15 are not used): - Octet m(0,1,2,3,8,9,10,11) → $\overline{B}$ - Quad m(0,4,8,12) → $\overline{C}\,\overline{D}$ $$ F = \overline{B} + \overline{C}\,\overline{D} $$ Check: the octet covers 0, 1, 8, 10, 11 and the quad covers 0, 4, 8, 12. #### Logic circuit $F$ needs one OR gate, one AND gate and inverters for B, C, D: ```text B ──[NOT]── B' ─────────────┐ [OR]── F C ──[NOT]── C' ──┐ │ [AND]─ C'D'┘ D ──[NOT]── D' ──┘ ``` Since $\overline{C}\,\overline{D} = \overline{C+D}$, the AND gate with two inverters can be replaced by a single NOR gate: ```text B ──[NOT]── B' ─────────┐ [OR]── F C ──┐ │ [NOR]── C'D' ───────┘ D ──┘ ``` The simplified circuit uses only 3 gates (NOT, NOR, OR), compared with 7 four-input AND terms for the unsimplified expression. | A B C D (example) | B' | C'D' | F | |---|---|---|---| | 0 1 0 0 (m4) | 0 | 1 | 1 | | 0 1 0 1 (m5) | 0 | 0 | 0 | | 1 0 1 1 (m11) | 1 | 0 | 1 | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does the octet m(0,1,2,3,8,9,10,11) reduce to? A. B B. B' C. C' D. A'B' Answer: B. All eight cells have B = 0, so the group is B'. (Key point: Octet from don't-cares) 2. What is F after K-map simplification? A. B' + C'D' B. B' + CD C. B + C'D' D. B'C'D' Answer: A. Octet gives B' and quad m(0,4,8,12) gives C'D'. (Key point: Simplified function) 3. Why can C'D' with two inverters be replaced by a single NOR gate? A. Because C'D' = (C+D)' B. Because C'D' = (CD)' C. Because NOR is an OR gate D. Because C'D' = C + D Answer: A. De Morgan: C'D' = (C+D)', so one NOR with inputs C and D gives the term. (Key point: Replacing AND with NOR) ## Close variants set in other exams - [Minterms/maxterms; K-map Σ(1,3,5,8,10,11,12)+d](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-1358) — Digital Logic, chapter 3, asked 2× ## Related in Digital Logic - [K-map ΠM(0,2,3,8,10,11,12,15)+d, NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-maxterm-nor-0238) — Digital Logic, chapter 3 - [K-map Σ(0,1,4,8,10,11,12)+d, NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-gates-01248) — Digital Logic, chapter 3, asked 5× - [K-map Σ(1,2,3,8,9,10,11,14)+d(0,4,12), NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-1238-dc-0412) — Digital Logic, chapter 3, asked 5× - [K-map Σ(0,1,4,8,10,11,12)+d, NAND-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-only-01248) — Digital Logic, chapter 3 - [K-map Σ(0,1,4,8,10,11,12)+d, standard minterm](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-standard-minterm-01248) — Digital Logic, chapter 3 - [K-map Π(0,1,4,7,8,10,11,12)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-maxterm-nand-0147) — Digital Logic, chapter 3 ## Related in other subjects - [Asphalt Institute design: 5.11×10⁴ ESAL/year, 12 years](https://www.bctengineer.com/question.md?key=semester_7%2Ftransportation_engineering_ii%3Aasphalt-institute-design-5-11e4-esal) — Transportation Engineering II, chapter 2 - [Q and center frequency; realize −2000/(s²+500s+10⁶)](https://www.bctengineer.com/question.md?key=semester_5%2Ffilter_design%3Atow-thomas-q-center-frequency-realize) — Filter Design, chapter 6 - [Tow-Thomas LPF derivation; realize −2000/(s²+500s+10⁶)](https://www.bctengineer.com/question.md?key=semester_5%2Ffilter_design%3Atow-thomas-realize-2000-tf) — Filter Design, chapter 6