---
title: "K-map F(M,N,O,P) in SOP using NAND"
subject: "Digital Logic"
chapter: 3
key: "semester_3/digital_logic:kmap-sop-nand-mnop"
source: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-sop-nand-mnop
site: BCT Engineering
---

# K-map F(M,N,O,P) in SOP using NAND

Digital Logic · Chapter 3: Combinational Logic Circuits

- Asked in: 2080 Baisakh, 4+2 marks
- Video: [Don't Care (X) Conditions in K-Map - Karnaugh Map ( Solved Examples ) - Design using NAND Gate only](https://www.youtube.com/watch?v=5OX-4g6kqTw) — CS Engineering Gyan
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/kmap-sop-nand-mnop
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3

## Question

Simplify the following expression using K-map. Express it in SOP format and realize it using NAND gate only. Y = F(M,N,O,P) = Σm(0,1,2,8,12,14,15) + d(5,10,11)

## Short answer

Simplified SOP: Y = MO + MP' + N'P' + M'N'O'. Realized with NAND gates by converting to NAND-NAND form, using inverters for complemented inputs.

## Answer

Given $Y = F(M,N,O,P) = \Sigma m(0,1,2,8,12,14,15) + d(5,10,11)$, with M as the MSB.

#### K-map simplification

```text
        OP
MN      00  01  11  10
      +---+---+---+---+
 00   | 1 | 1 | 0 | 1 |
      +---+---+---+---+
 01   | 0 | X | 0 | 0 |
      +---+---+---+---+
 11   | 1 | 0 | 1 | 1 |
      +---+---+---+---+
 10   | 1 | 0 | X | X |
      +---+---+---+---+
```

- Quad m(10,11,14,15) → $MO$
- Quad m(8,10,12,14) → $M\overline{P}$
- Quad m(0,2,8,10) → $\overline{N}\,\overline{P}$
- Pair m(0,1) → $\overline{M}\,\overline{N}\,\overline{O}$

#### SOP form

$$
Y = MO + M\overline{P} + \overline{N}\,\overline{P} + \overline{M}\,\overline{N}\,\overline{O}
$$

Check: 14, 15 by $MO$ (with 10, 11); 8, 12, 14 by $M\overline{P}$; 0, 2, 8 by $\overline{N}\,\overline{P}$ (with 10); 1 by $\overline{M}\,\overline{N}\,\overline{O}$. ($\overline{M}\,\overline{O}P$, cells 1 and 5, is an equally good choice for the last term.)

#### Realization using NAND gates only

An SOP expression maps directly to a two-level NAND-NAND circuit (De Morgan: $X + Y = \overline{\overline{X}\cdot\overline{Y}}$). Each product term becomes a first-level NAND and the output NAND replaces the OR gate. Complemented inputs are made with NAND gates whose inputs are tied.

$$
Y = \overline{\overline{MO}\cdot\overline{M\overline{P}}\cdot\overline{\overline{N}\,\overline{P}}\cdot\overline{\overline{M}\,\overline{N}\,\overline{O}}}
$$

```text
M ──[NAND]── M'   (inputs tied)
N ──[NAND]── N'   (inputs tied)
O ──[NAND]── O'   (inputs tied)
P ──[NAND]── P'   (inputs tied)

M, O       ──[NAND]── G1  ─┐
M, P'      ──[NAND]── G2  ─┤
                           ├──[NAND]── Y
N', P'     ──[NAND]── G3  ─┤
M', N', O' ──[NAND]── G4  ─┘
```

Gates: 4 NAND inverters, 4 first-level NANDs and one 4-input output NAND.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In Y = F(M,N,O,P), which variable is the MSB?
   A. P
   B. M
   C. N
   D. O
   Answer: B. M is the MSB, so minterm numbers are read as MNOP. (Key point: MSB convention)

2. Which term does m(10,11,14,15) give?
   A. MO
   B. MP'
   C. NO
   D. M'O
   Answer: A. These cells all have M=1 and O=1, giving MO. (Key point: Quad for 10,11,14,15)

3. What is Y?
   A. MO + MP' + N'P' + M'N'O'
   B. MO + NP + M'O'
   C. M + N'P'
   D. MO + MP' + N'P'
   Answer: A. Four terms: MO, MP', N'P' and M'N'O' (to cover minterm 1). (Key point: Minimal SOP)

4. How many NAND gates does the circuit use?
   A. 5
   B. 9
   C. 6
   D. 10
   Answer: B. 4 inverters + 4 first-level NANDs + 1 four-input output NAND = 9. (Key point: NAND-only gate count)

## Related in Digital Logic

- [K-map Σ(1,2,3,8,9,10,11,14)+d(0,4,12), NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-1238-dc-0412) — Digital Logic, chapter 3, asked 5×
- [K-map Σ(0,1,4,8,10,11,12)+d, NAND-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-only-01248) — Digital Logic, chapter 3
- [K-map Π(0,1,4,7,8,10,11,12)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-maxterm-nand-0147) — Digital Logic, chapter 3
- [K-map Σm(7,9,12,13,14,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-sum-7-9-12) — Digital Logic, chapter 3
- [K-map Σ(0,1,4,8,10,11,12)+d, realize circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-realize-circuit-01248) — Digital Logic, chapter 3, asked 2×
- [K-map ΠM(0,2,3,8,10,11,12,15)+d, NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-maxterm-nor-0238) — Digital Logic, chapter 3

## Related in other subjects

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- [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6
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