--- title: "Master-slave JK flip-flop" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:master-slave-jk" source: https://www.bctengineer.com/q/semester_3/digital_logic/master-slave-jk site: BCT Engineering --- # Master-slave JK flip-flop Digital Logic · Chapter 6: Flip Flops - Asked in: 2076 Chaitra, 2+4 marks - Video: [Master Slave JK Flip Flop](https://www.youtube.com/watch?v=t2LZtaNck_g) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/master-slave-jk - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Differentiate between combinational and sequential circuit. Explain working principle of master slave JK flip-flop. ## Short answer Combinational circuits have no memory, outputs depend only on current inputs; sequential circuits have memory and feedback, often clocked. A master-slave JK flip-flop uses two latches: the master samples J,K when CLK=1, and the slave copies the master at the falling edge. This prevents output feedback from causing multiple toggles (race-around). ## Answer #### Combinational vs sequential circuit | Point | Combinational circuit | Sequential circuit | |---|---|---| | Output depends on | Present inputs only | Present inputs and past state | | Memory | No memory element | Has memory (latches, flip-flops) | | Feedback | No feedback path | Output fed back to input | | Clock | Not needed | Usually needed (synchronous) | | Described by | Truth table | State table / state diagram | | Examples | Adder, MUX, decoder | Flip-flop, register, counter | #### Master-slave J-K flip-flop A **master-slave J-K flip-flop** is two clocked latches in series: the **master** is enabled by CLK and the **slave** by the inverted clock CLK'. The final outputs Q and Q' are fed back to the master's input gates. It was designed to remove the **race-around condition** of the level-triggered J-K flip-flop. ```text +---------+ Qm +---------+ J -----| MASTER |------->| SLAVE |----> Q | SR latch| | SR latch| K -----| (gated) |------->| (gated) |----> Q' +---------+ Qm' +---------+ ^ ^ CLK --------+-----[NOT]--------+ Master enabled when CLK=1, slave when CLK=0. Q' is fed back to the J gate and Q to the K gate of the master. ``` **Working principle** 1. **CLK = 1 (master active, slave disabled):** the master reads J, K and the fed-back Q, Q' and sets its outputs Qm, Qm' (J = 1, K = 0 sets Qm; J = 0, K = 1 resets Qm; J = K = 1 makes Qm the complement of Q; J = K = 0 holds). The slave is closed, so **Q does not change**. 2. **CLK goes 1 to 0:** the master is disabled and freezes Qm. The slave becomes enabled. 3. **CLK = 0 (slave active):** the slave copies the master (Q = Qm). Since the master is closed, changing Q cannot affect the master during this time. 4. So the output changes only once per clock pulse, at the **falling edge**, and Q never feeds back into an active master. Toggling for J = K = 1 happens only once, which **removes race-around**. | J | K | Q after falling edge | |---|---|---| | 0 | 0 | Q (no change) | | 0 | 1 | 0 (reset) | | 1 | 0 | 1 (set) | | 1 | 1 | Q' (toggle once) | ```text CLK __|‾‾‾‾|____|‾‾‾‾|____ Qm __|‾‾‾‾‾‾‾‾‾|________ (J = K = 1) Q _______|‾‾‾‾‾‾‾‾‾|____ master slave copies at falling edge ``` A drawback is that J and K must not change while CLK = 1 (the master can "catch" a 1), so the inputs should be stable during the high period. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What distinguishes a sequential circuit from a combinational one? A. Output depends only on present inputs B. Output depends on present inputs and past state, using memory C. It has no feedback D. It never uses a clock Answer: B. Sequential circuits have memory elements, so outputs depend on past state as well. (Key point: Sequential vs combinational) 2. When are the master and slave latches enabled? A. Both when CLK = 1 B. Master when CLK = 1, slave when CLK = 0 C. Master when CLK = 0, slave when CLK = 1 D. Both when CLK = 0 Answer: B. The master uses CLK and the slave uses inverted CLK. (Key point: Master and slave enable) 3. When does the master-slave J-K output Q change? A. During the whole high period B. At the falling edge of the clock, when the slave copies the master C. At the rising edge only D. Never Answer: B. The master freezes as CLK falls and the slave then copies it. (Key point: Output change time) 4. Why does master-slave remove race-around? A. The slave is always disabled B. Q cannot feed back into an active master, so it toggles only once per pulse C. J and K are ignored D. The clock is shorter Answer: B. When Q changes the master is closed, so the change cannot cause a second toggle. (Key point: Race-around removal) ## Related in Digital Logic - [Edge triggered JK flip-flop circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-circuit) — Digital Logic, chapter 6 - [Positive edge JK flip-flop and its drawbacks](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apositive-edge-jk-drawbacks) — Digital Logic, chapter 6 - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× - [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [JK flip-flop characteristic and excitation tables](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-characteristic-excitation) — Digital Logic, chapter 6, asked 2× - [T to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3At-to-jk-conversion) — Digital Logic, chapter 6, asked 2× ## Related in other subjects - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9 - [VHDL COMPONENT; JK flip-flop with PROCESS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-component-jk-ff) — Embedded System, chapter 9