--- title: "Mealy detector for 010 using JK" subject: "Digital Logic" chapter: 9 key: "semester_3/digital_logic:mealy-detector-010-jk" source: https://www.bctengineer.com/q/semester_3/digital_logic/mealy-detector-010-jk site: BCT Engineering --- # Mealy detector for 010 using JK Digital Logic · Chapter 9: Sequential Machines - Asked in: 2076 Chaitra, 10 marks - Video: [010 and 11 Sequence Detector Using Melay FSM|Multiple sequence detector using Melay FSM](https://www.youtube.com/watch?v=yG67To4DZl8) — Easy Electronics - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mealy-detector-010-jk - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9 ## Question Using Mealy circuit with J-K flip-flops design a synchronous sequence detector that produces output Z=1 when it detects the serial input X=010. ## Short answer A Mealy machine with states A(00), B(01), C(10) detects overlapping '010'. J-K flip-flop excitation yields J1 = Q0 X, K1 = 1, J0 = X', K0 = X, output Z = Q1 X'. ## Answer A **Mealy** machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of **010** arrives. Flip-flops: **J-K**. States (what has been received so far): - **A**: reset / no useful bits - **B**: "0" received - **C**: "01" received #### State diagram (Mealy) ```text Arc label = input/output A --0/0--> B --1/0--> C --0/1--> B A --1/0--> A (self loop) B --0/0--> B (self loop) C --1/0--> A ``` #### State table | Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) | |---|---|---|---|---| | A | B | A | 0 | 0 | | B | B | C | 0 | 0 | | C | B | A | 1 | 0 | #### State assignment A = 00, B = 01, C = 10 (flip-flop outputs $Q_1 Q_0$). The unused code 11 is taken as don't care (x) in all K-maps. The flip-flops are cleared to 00 at power-on (start state). Checking the final equations, from 11 the machine goes to a valid state on the next clock (X=0 goes to B, X=1 goes to A), so it is self-starting. #### Excitation table of J-K flip-flop | Q | Q+ | J | K | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | x | | 1 | 0 | x | 1 | | 1 | 1 | x | 0 | #### Transition and excitation table | Q1 Q0 | X | Q1+ Q0+ | J1 | K1 | J0 | K0 | Z | |---|---|---|---|---|---|---|---| | 0 0 | 0 | 0 1 | 0 | x | 1 | x | 0 | | 0 0 | 1 | 0 0 | 0 | x | 0 | x | 0 | | 0 1 | 0 | 0 1 | 0 | x | x | 0 | 0 | | 0 1 | 1 | 1 0 | 1 | x | x | 1 | 0 | | 1 0 | 0 | 0 1 | x | 1 | 1 | x | 1 | | 1 0 | 1 | 0 0 | x | 1 | 0 | x | 0 | #### K-maps and simplified equations ```text J1 X=0 X=1 Q1Q0=00 0 0 Q1Q0=01 0 1 Q1Q0=11 x x Q1Q0=10 x x K1 X=0 X=1 Q1Q0=00 x x Q1Q0=01 x x Q1Q0=11 x x Q1Q0=10 1 1 J0 X=0 X=1 Q1Q0=00 1 0 Q1Q0=01 x x Q1Q0=11 x x Q1Q0=10 1 0 K0 X=0 X=1 Q1Q0=00 x x Q1Q0=01 0 1 Q1Q0=11 x x Q1Q0=10 x x Z X=0 X=1 Q1Q0=00 0 0 Q1Q0=01 0 0 Q1Q0=11 x x Q1Q0=10 1 0 ``` $$ \begin{aligned} J_1 &= Q_0 X \\ K_1 &= 1 \\ J_0 &= X' \\ K_0 &= X \\ Z &= Q_1 X' \end{aligned} $$ #### Logic diagram ```text +-------------+ +----------+ X ------>| next-state |---->| FF1, FF0 |--+--> Q1, Q0 +----->| logic | | (CLK) | | | +-------------+ +----------+ | +-------------------<--------------------+ | +-------------+ +----->| output |----> Z X ------>| logic | +-------------+ ``` Gates needed (two J-K flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates): - $J_1$: a 2-input AND for $Q_0 X$. - $K_1$: tied to logic 1. - $J_0$: direct line $X'$. - $K_0$: direct line $X$. - $Z$: a 2-input AND for $Q_1 X'$. **Check:** input X = 1010101 gives Z = 0001010; Z = 1 at bits 4 and 6 (overlapping 01010). After 010 the tail "0" is kept, so C goes to B on 0. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why does C --0/1--> B on detection? A. The trailing 0 can start another 010 B. C returns to the reset state C. The 0 resets the machine D. Overlap is not allowed Answer: A. The last 0 of 010 is the first 0 of a new 010, so the tail 0 is kept (state B). (Key point: Overlap) 2. What does B do on X=0? A. Goes to A B. Stays in B C. Goes to C D. Outputs 1 Answer: B. A further 0 leaves a useful tail '0', so it stays in B. (Key point: State B) 3. Which equations were found? A. J1 = Q0 X', K1 = X, J0 = X, K0 = 1 B. J1 = X, K1 = 0, J0 = Q1, K0 = X' C. J1 = Q0 X, K1 = 1, J0 = X', K0 = X D. J1 = Q1 X, K1 = X', J0 = X, K0 = 1 Answer: C. From the K-maps: J1 = Q0 X, K1 = 1, J0 = X', K0 = X, Z = Q1 X'. (Key point: Equations) 4. For X = 1010101, where is Z = 1? A. Bits 3 and 5 B. Bit 4 only C. Bits 5 and 7 D. Bits 4 and 6 Answer: D. Z = 0001010, each 010 ends at bit 4 and bit 6. (Key point: Check) ## Close variants set in other exams - [Mealy detector for 110 using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amealy-detector-110-jk) — Digital Logic, chapter 9, asked 2× ## Related in Digital Logic - [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7× - [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7× - [Sequence detector 110 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-jk) — Digital Logic, chapter 9, asked 3× - [Sequence detector 1101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-t) — Digital Logic, chapter 9, asked 7× - [Sequence detector 1110 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1110-t) — Digital Logic, chapter 9, asked 7× - [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3× ## Related in other subjects - [VHDL entity declaration; T flip-flops circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-two-tff-inverter) — Embedded System, chapter 9 - [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×