--- title: "Minimize 9-term SOP and implement in NAND" subject: "Digital Logic" chapter: 3 key: "semester_3/digital_logic:minimize-nine-term-nand" source: https://www.bctengineer.com/q/semester_3/digital_logic/minimize-nine-term-nand site: BCT Engineering --- # Minimize 9-term SOP and implement in NAND Digital Logic · Chapter 3: Combinational Logic Circuits - Asked in: 2074 Chaitra, 4+2 marks - Video: [Implementing Boolean Expressions Using NAND Gates | Logic GATEs](https://www.youtube.com/watch?v=ycPH_DRIfHQ) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/minimize-nine-term-nand - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3 ## Question Minimize the expression and implement the reduced expression by using NAND gates. F = A'BC'D' + A'BC'D + A'BCD + A'BCD' + AB'C'D' + AB'C'D + AB'CD' + ABC'D' + ABCD' ## Short answer The minimized expression is F = A'B + AD' + AB'C'. Implement with NAND gates: use NAND inverters for A', B', C', D', then three NAND gates for (A' B)', (A D')', and (A B' C')', and a final NAND to combine them. ## Answer #### Minterm numbers Write each term as a binary number ABCD: | Term | ABCD | Minterm | |---|---|---| | $\overline{A}B\overline{C}\,\overline{D}$ | 0100 | 4 | | $\overline{A}B\overline{C}D$ | 0101 | 5 | | $\overline{A}BCD$ | 0111 | 7 | | $\overline{A}BC\overline{D}$ | 0110 | 6 | | $A\overline{B}\,\overline{C}\,\overline{D}$ | 1000 | 8 | | $A\overline{B}\,\overline{C}D$ | 1001 | 9 | | $A\overline{B}C\overline{D}$ | 1010 | 10 | | $AB\overline{C}\,\overline{D}$ | 1100 | 12 | | $ABC\overline{D}$ | 1110 | 14 | $$ F = \Sigma m(4,5,6,7,8,9,10,12,14) $$ #### K-map minimization ```text CD AB 00 01 11 10 +---+---+---+---+ 00 | 0 | 0 | 0 | 0 | +---+---+---+---+ 01 | 1 | 1 | 1 | 1 | +---+---+---+---+ 11 | 1 | 0 | 0 | 1 | +---+---+---+---+ 10 | 1 | 1 | 0 | 1 | +---+---+---+---+ ``` - Quad m(4,5,6,7) → $\overline{A}B$ - Quad m(8,10,12,14) → $A\overline{D}$ - Pair m(8,9) → $A\overline{B}\,\overline{C}$ $$ F = \overline{A}B + A\overline{D} + A\overline{B}\,\overline{C} $$ Check: row 01 is covered by $\overline{A}B$; 8, 10, 12, 14 by $A\overline{D}$; 9 (with 8) by $A\overline{B}\,\overline{C}$. The 9-term, 36-literal expression reduces to 3 terms and 7 literals. #### NAND implementation An SOP expression maps directly to a two-level NAND-NAND circuit: $$ F = \overline{\overline{\overline{A}B}\cdot\overline{A\overline{D}}\cdot\overline{A\overline{B}\,\overline{C}}} $$ ```text A ──[NAND]── A' (inputs tied) B ──[NAND]── B' (inputs tied) C ──[NAND]── C' (inputs tied) D ──[NAND]── D' (inputs tied) A', B ──[NAND]── P1 ─┐ A, D' ──[NAND]── P2 ─┤──[NAND]── F A, B', C' ──[NAND]── P3 ─┘ ``` Gates: 4 NAND inverters (for $\overline{A}, \overline{B}, \overline{C}, \overline{D}$), three first-level NANDs (two 2-input, one 3-input) and one 3-input output NAND. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the minterm number of the term A'BC'D' (ABCD)? A. 2 B. 8 C. 5 D. 4 Answer: D. A'BC'D' = 0100 in binary, which is decimal 4. (Key point: Minterm conversion) 2. Which grouping covers minterms 8, 10, 12 and 14 in the K-map? A. A'B B. AD' C. BD' D. AB'C' Answer: B. Cells 8,10,12,14 all have A=1 and D=0, so the quad gives A D'. (Key point: K-map groups) 3. What is the minimal SOP for F = Σm(4,5,6,7,8,9,10,12,14)? A. A'B + AD' + AB'C' B. A'B + AD' + B'C' C. A'B + AD' D. A + B + D' Answer: A. A'B covers 4-7, AD' covers 8,10,12,14, and AB'C' is needed for minterm 9. (Key point: Minimal expression) 4. Why does an SOP expression map directly to a two-level NAND-NAND circuit? A. Because NAND gates cannot be used for inverters B. Because X + Y = (X'·Y')', so first-level NANDs form products and the output NAND acts as the OR C. Because AND-OR needs more gates than NAND D. Because NAND gates ignore complemented inputs Answer: B. De Morgan's law turns the OR of product terms into a NAND of NANDed products. (Key point: NAND-NAND realization) ## Related in Digital Logic - [SOP/POS forms and canonical form of A+BC+ABC](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asop-pos-canonical-form) — Digital Logic, chapter 3 - [K-map F(M,N,O,P) in SOP using NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-sop-nand-mnop) — Digital Logic, chapter 3 - [XOR gate using minimum NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Axor-using-nand-only) — Digital Logic, chapter 2, asked 2× - [3-input XOR using NAND gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xor-nand) — Digital Logic, chapter 2, asked 2× - [Universal gates; Ex-OR using NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Auniversal-gates-xor-nand) — Digital Logic, chapter 2 - [Why NAND and NOR are universal gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Auniversal-gates-why) — Digital Logic, chapter 2 ## Related in other subjects - [Design pipelines AB, BC and CD, C = 120](https://www.bctengineer.com/question.md?key=semester_5%2Fwater_supply_engineering%3Apd-c74) — Water Supply Engineering, chapter 7 - [Hardy-Cross network discharge AB, BC, AD, CD](https://www.bctengineer.com/question.md?key=semester_5%2Fwater_supply_engineering%3Ahardy-cross-as69) — Water Supply Engineering, chapter 7 - [Head loss and velocity in loop pipes AB, BC, AC, CD](https://www.bctengineer.com/question.md?key=semester_5%2Fwater_supply_engineering%3Aloop-c73) — Water Supply Engineering, chapter 7 - [K-map: A'BC' + ABC' + ABC](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-abc-three-term) — Basic Electronics Engineering, chapter 6