--- title: "Minterms/maxterms; K-map Σm(2,4,5,13,14)+d, universal gates" subject: "Digital Logic" chapter: 3 key: "semester_3/digital_logic:minterm-maxterm-kmap-universal" source: https://www.bctengineer.com/q/semester_3/digital_logic/minterm-maxterm-kmap-universal site: BCT Engineering --- # Minterms/maxterms; K-map Σm(2,4,5,13,14)+d, universal gates Digital Logic · Chapter 3: Combinational Logic Circuits - Asked in: 2082 Baisakh, 2+6 marks - Video: [Minimize the following expression using K map and realize using NOR gate](https://www.youtube.com/watch?v=2HpvaRRDPK8) — Maharshi Sanand Yadav T - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/minterm-maxterm-kmap-universal - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-3 ## Question Define the minterm and maxterm. Simplify the boolean function F = Σm(2,4,5,13,14) + dΣm(0,1,8,10) and draw its logic diagram of the simplified boolean function using universal gates only. ## Short answer A minterm is an AND term containing all variables, true for one combination; a maxterm is an OR term containing all variables, false for one combination. Simplified: F = A'C' + B'D' + BC'D + ACD'. Realized with NAND gates using two-level NAND-NAND circuit. ## Answer #### Minterm and maxterm A **minterm** is a product (AND) term that contains every variable of the function exactly once, in true or complemented form. It equals 1 for exactly one input combination. A variable is written true if its value is 1 and complemented if it is 0; e.g. for ABC = 101 the minterm is $m_5 = A\overline{B}C$. A function in **canonical SOP** is a sum of minterms: $F = \Sigma m(\dots)$. A **maxterm** is a sum (OR) term that contains every variable exactly once, in true or complemented form. It equals 0 for exactly one input combination. A variable is written true if its value is 0 and complemented if it is 1; e.g. for ABC = 101 the maxterm is $M_5 = \overline{A}+B+\overline{C}$. A function in **canonical POS** is a product of maxterms: $F = \Pi M(\dots)$. $M_i = \overline{m_i}$, and a function's minterm list and maxterm list are complementary (together they hold all $2^n$ numbers). #### Simplification by K-map $F(A,B,C,D) = \Sigma m(2,4,5,13,14) + d(0,1,8,10)$ ```text CD AB 00 01 11 10 +---+---+---+---+ 00 | X | X | 0 | 1 | +---+---+---+---+ 01 | 1 | 1 | 0 | 0 | +---+---+---+---+ 11 | 0 | 1 | 0 | 1 | +---+---+---+---+ 10 | X | 0 | 0 | X | +---+---+---+---+ ``` - Quad m(0,1,4,5) → $\overline{A}\,\overline{C}$ - Quad m(0,2,8,10) → $\overline{B}\,\overline{D}$ - Pair m(5,13) → $B\overline{C}D$ - Pair m(10,14) → $AC\overline{D}$ $$ F = \overline{A}\,\overline{C} + \overline{B}\,\overline{D} + B\overline{C}D + AC\overline{D} $$ Check: 4, 5 by $\overline{A}\,\overline{C}$ (with 0, 1); 2 by $\overline{B}\,\overline{D}$ (with 0, 8, 10); 13 by $B\overline{C}D$; 14 by $AC\overline{D}$ (with 10). This is a minimal cover (4 terms, 10 literals); the minimal POS also needs 4 terms and 10 literals, so the SOP form is used. #### Logic diagram using universal gates (NAND only) An SOP expression maps directly to a two-level NAND-NAND circuit (De Morgan: $X + Y = \overline{\overline{X}\cdot\overline{Y}}$). Each product term becomes a first-level NAND and the output NAND replaces the OR gate. Complemented inputs are made with NAND gates whose inputs are tied. $$ F = \overline{\overline{\overline{A}\,\overline{C}}\cdot\overline{\overline{B}\,\overline{D}}\cdot\overline{B\overline{C}D}\cdot\overline{AC\overline{D}}} $$ ```text A ──[NAND]── A' (inputs tied) B ──[NAND]── B' (inputs tied) C ──[NAND]── C' (inputs tied) D ──[NAND]── D' (inputs tied) A', C' ──[NAND]── P1 ─┐ B', D' ──[NAND]── P2 ─┤ ├──[NAND]── F B, C', D ──[NAND]── P3 ─┤ A, C, D' ──[NAND]── P4 ─┘ ``` Gates: 4 NAND inverters, two 2-input NANDs, two 3-input NANDs and one 4-input output NAND (9 NAND gates). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which statement describes a minterm? A. A product term with all variables, equal to 1 for exactly one input combination B. A sum term with all variables, equal to 0 for exactly one combination C. A product term equal to 0 for one combination D. A sum term equal to 1 for one combination Answer: A. A minterm is an AND of all variables and is 1 at only one combination. (Key point: Minterm definition) 2. Which groups cover F = Σm(2,4,5,13,14) + d(0,1,8,10)? A. A'C', B'D', BC'D and ACD' B. A'B', CD, BD and AC C. A'C', B'D', BC and AD' D. A'D', B'C', BD and AC Answer: A. Quad 0,1,4,5 = A'C'; quad 0,2,8,10 = B'D'; pair 5,13 = BC'D; pair 10,14 = ACD'. (Key point: K-map groups) 3. Why is the SOP form used for the final circuit? A. POS is not possible B. The minimal POS also needs 4 terms and 10 literals, so SOP is as good and maps to NAND-NAND C. SOP has fewer literals than POS D. Only SOP can be built with universal gates Answer: B. Both forms cost the same, so the SOP form is used and gives a direct NAND-NAND circuit. (Key point: Reason for SOP choice) 4. How many NAND gates are needed for the NAND-only diagram? A. 9 B. 5 C. 4 D. 13 Answer: A. 4 inverters + four first-level NANDs (two 2-input, two 3-input) + one 4-input output NAND = 9. (Key point: Gate count) ## Related in Digital Logic - [Minterms/maxterms; K-map Σm(0,1,2,4,6,8,9,12,13,14)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-01246) — Digital Logic, chapter 3 - [Minterms/maxterms; K-map Σm(0,1,2,5,8,14)+d, NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-nor-0125) — Digital Logic, chapter 3 - [K-map Σm(7,9,12,13,14,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-sum-7-9-12) — Digital Logic, chapter 3 - [Minterms/maxterms; K-map Σm(0,1,2,4,5,9,12,15)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-nand-0124) — Digital Logic, chapter 3 - [Minterms/maxterms; K-map Σ(1,3,5,8,10,11,12)+d](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-1358) — Digital Logic, chapter 3, asked 2× - [K-map Σ(1,2,3,8,9,10,11,13,14)+d, POS](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-pos-form-12389) — Digital Logic, chapter 3 ## Related in other subjects - [K-map and universal gate: xy + x'z + yz](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-universal-gate-xy) — Basic Electronics Engineering, chapter 6 - [K-map with don't cares, NAND only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-dont-care-nand) — Basic Electronics Engineering, chapter 6 - [K-map: 4-variable minterm list](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-4var-sigma) — Basic Electronics Engineering, chapter 6 - [K-map: x'yz + x'y'z + xyz with gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-xyz-realize-gates) — Basic Electronics Engineering, chapter 6, asked 2×